test_filter.v

来自「插值滤波器,用于音频解码调制解调,滤波器系数用移位相加实现」· Verilog 代码 · 共 12 行

module test_filter(data_out);

output [18:1] data_out;

wire [18:1] data_in;
wire clock,reset;
wire [4:1] control;

top_core_sign top_core_sign(data_in,clock,reset,control);
filter filter(data_in,clock,reset,control,data_out);

endmodule