test_top.v

来自「插值滤波器,用于音频解码调制解调,滤波器系数用移位相加实现」· Verilog 代码 · 共 33 行

`timescale 1ns/10ps
module test_top(data_out);

output [18:1] data_out;

wire [18:1] data_in;
wire clock,reset;
wire [4:1] control;
//wire [18:1] hf_out,multi_out;
integer fid;

top_total_sign top_total_sign(data_in,clock,reset,control,save);
top_total top_total(data_in,clock,reset,control,data_out);
//filter filter(data_in,clock,reset,data_out);
//top_half1 top_half1(data_in,clock1,reset,hf_out);
//top_multi1 top_multi1(hf_out,clock2,reset,multi_out);
//top_sh top_sh(multi_out,clock3,reset,data_out);

initial
  begin
    $monitor("%d %d",save,data_in);
    //fid = $fopen("e:/MATLAB6p5/work/total(10000).dat");
    fid = $fopen("e:/data_in.dat");
  end
    always @(posedge save) 
      begin
          if(save) 
             begin 
             $fwrite(fid,"%h\n",data_in[16:1]);
             end
       end      
endmodule