📄 startup.lst
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156 1 ; SFR symbol definition
157 1 ;******************************************************************************
158 1 ;------------------------------------------------------------------------------
159 1 ; processor mode register0
160 1 ;------------------------------------------------------------------------------
161 00000004h 1 pm0 .equ 00004H
162 1 ;------------------------------------------------------------------------------
163 1 ; processor mode register1
164 1 ;------------------------------------------------------------------------------
165 00000005h 1 pm1 .equ 00005H
166 1 ;------------------------------------------------------------------------------
167 1 ; system clock control register0
168 1 ;------------------------------------------------------------------------------
169 00000006h 1 cm0 .equ 00006H
170 1 ;------------------------------------------------------------------------------
171 1 ; system clock control register1
172 1 ;------------------------------------------------------------------------------
173 00000007h 1 cm1 .equ 00007H
174 1 ;------------------------------------------------------------------------------
175 1 ; protect register
176 1 ;------------------------------------------------------------------------------
177 0000000Ah 1 prcr .equ 0000AH
178 1
179 0,0000000Ah 1 prc0 .btequ 0,prcr ; system clock control register0,1
180 1 ; write-enable bit
181 1,0000000Ah 1 prc1 .btequ 1,prcr ; processor mode register0,1
182 1 ; write-enable bit
183 1 ;------------------------------------------------------------------------------
184 1 ; port P0 direction register
185 1 ;------------------------------------------------------------------------------
186 000003E2h 1 pd0 .equ 003E2H
* R8C/Tiny,M16C SERIES ASSEMBLER * SOURCE LIST Tue Oct 14 16:11:38 2008 PAGE 004
SEQ. LOC. OBJ. 0XMSDA ....*....SOURCE STATEMENT....7....*....8....*....9....*....0....*....1....*....2....*....3....*....4
187 1 ;------------------------------------------------------------------------------
188 1 ; port P1 direction register
189 1 ;------------------------------------------------------------------------------
190 000003E3h 1 pd1 .equ 003E3H
191 1 ;------------------------------------------------------------------------------
192 1 ; port P2 direction register
193 1 ;------------------------------------------------------------------------------
194 000003E6h 1 pd2 .equ 003E6H
195 1 ;------------------------------------------------------------------------------
196 1 ; port P3register
197 1 ;------------------------------------------------------------------------------
198 000003E5h 1 p3 .equ 003E5H
199 1 ;------------------------------------------------------------------------------
200 1 ; port P3 direction register
201 1 ;------------------------------------------------------------------------------
202 000003E7h 1 pd3 .equ 003E7H
203 1 ;------------------------------------------------------------------------------
204 1 ; port P4 register
205 1 ;------------------------------------------------------------------------------
206 000003E8h 1 p4 .equ 003E8H
207 1
208 4,000003E8h 1 p4_4 .btequ 4,003E8H ; port P4 bit 4
209 5,000003E8h 1 p4_5 .btequ 5,003E8H ; port P4 bit 5
210 6,000003E8h 1 p4_6 .btequ 6,003E8H ; port P4 bit 6
211 1 ;------------------------------------------------------------------------------
212 1 ; port P4 direction register
213 1 ;------------------------------------------------------------------------------
214 000003EAh 1 pd4 .equ 003EAH ; port P4 direction register
215 1 ;------------------------------------------------------------------------------
216 1 ; port P5 direction register
217 1 ;------------------------------------------------------------------------------
218 000003EBh 1 pd5 .equ 003EBH
219 1 ;------------------------------------------------------------------------------
220 1 ; port P6 direction register
221 1 ;------------------------------------------------------------------------------
222 000003EEh 1 pd6 .equ 003EEH
223 1 ;------------------------------------------------------------------------------
224 1 ; port P7 register
225 1 ;------------------------------------------------------------------------------
226 000003EDh 1 p7 .equ 003EDH
227 1 ;------------------------------------------------------------------------------
228 1 ; port P7 direction register
229 1 ;------------------------------------------------------------------------------
230 000003EFh 1 pd7 .equ 003EFH
231 1 ;------------------------------------------------------------------------------
232 1 ; port P8 register
233 1 ;------------------------------------------------------------------------------
234 000003F0h 1 p8 .equ 003F0H
235 1 ;------------------------------------------------------------------------------
236 1 ; port P8 direction register
237 1 ;------------------------------------------------------------------------------
238 000003F2h 1 pd8 .equ 003F2H
239 1 ;------------------------------------------------------------------------------
240 1 ; port P9 direction register
241 1 ;------------------------------------------------------------------------------
242 000003F3h 1 pd9 .equ 003F3H
243 1 ;------------------------------------------------------------------------------
244 1 ; port P10 direction register
245 1 ;------------------------------------------------------------------------------
246 000003F6h 1 pd10 .equ 003F6H
247 1
248 1 ;******************************************************************************
* R8C/Tiny,M16C SERIES ASSEMBLER * SOURCE LIST Tue Oct 14 16:11:38 2008 PAGE 005
SEQ. LOC. OBJ. 0XMSDA ....*....SOURCE STATEMENT....7....*....8....*....9....*....0....*....1....*....2....*....3....*....4
249 1 ; end of file
250 1 ;******************************************************************************
251 ; SFR defining file
252 ;==============================================================================
253 ; macro definition
254 ;==============================================================================
255 ;-------------------------------------------------------------------------------
256 ; macro definition for clearing static variable area without initial value (for far)
257 ; if _bzero is used, you must link nc30lib.lib.
258 ;-------------------------------------------------------------------------------
259 D BZERO .macro TOP_,SECT_
260 D push.w #sizeof SECT_ >> 16
261 D push.w #sizeof SECT_ & 0ffffh
262 D pusha TOP_ >>16
263 D pusha TOP_ & 0ffffh
264 D .stk 8
265 D .glb _bzero
266 D .call _bzero,G
267 D jsr.a _bzero
268 D add.b #08,SP
269 .endm
270 ;-------------------------------------------------------------------------------
271 ; macro definition for transfering initial values into static variable area
272 ; with initial value (for far area)
273 ; if _bcopy is used, you must link nc30lib.lib.
274 ;-------------------------------------------------------------------------------
275 D BCOPY .macro FROM_ ,TO_ ,SECT_
276 D push.w #sizeof SECT_ >> 16
277 D push.w #sizeof SECT_ & 0ffffh
278 D pusha TO_ >>16
279 D pusha TO_ & 0ffffh
280 D pusha FROM_ >>16
281 D pusha FROM_ & 0ffffh
282 D .stk 12
283 D .glb _bcopy
284 D .call _bcopy,G
285 D jsr.a _bcopy
286 D add.b #12,SP
287 .endm
288 ;==============================================================================
289 ; startup program area
290 ;==============================================================================
291 .section startup ;
292 ;
293 .glb start
294 .glb _main
295 .glb _exit
296 .glb $exit
297 00000 start: ; start address of startup program
298 ;
299 00000 EB400000r ldc #STACK_INI,ISP ; initialize ISP
300
301 ;===== when write flash memory, please delete the following comment ";". =====
302 ;
303 ; ----- initialization of processor mode register -----
304 ; bset prc1 ; processor mode register 0,1
305 ; ; write-enabled
306 ; mov.b #00000000B,pm0 ; single-chip mode
307 ; mov.b #00000000B,pm1 ; non-expansion, no wait
308 ; bclr prc1 ; processor mode register 0,1
309 ; ; write-inhibited
310 ; ----- initialization of system clock control register -----
* R8C/Tiny,M16C SERIES ASSEMBLER * SOURCE LIST Tue Oct 14 16:11:38 2008 PAGE 006
SEQ. LOC. OBJ. 0XMSDA ....*....SOURCE STATEMENT....7....*....8....*....9....*....0....*....1....*....2....*....3....*....4
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