📄 control.lst
字号:
C51 COMPILER V7.06 CONTROL 06/13/2005 12:55:38 PAGE 1
C51 COMPILER V7.06, COMPILATION OF MODULE CONTROL
OBJECT MODULE PLACED IN control.OBJ
COMPILER INVOKED BY: D:\Keil\C51\BIN\c51.exe control.c DB OE
stmt level source
1 /*********************************************************************************************************
-*
2 Sincere Techonlogy
3 Shanghai.China
4 (c) Copyright 2005,Sincere Technology,Shanghai China
5 All Rights Reserved
6
7
8
9 File name : control.c
10 Author : Neil
11 Description : All of the digital peripherals control codes is in this file.
12 Target : C8051F023
13 Data : 2005-3
14 **********************************************************************************************************
-/
15 #define CTONL_C
16
17 #include "Include.h"
18
19 /*********************************************************************************************************
20 ----------------------------------------------------------------------------------------------------------
21 void DELAY (int i)
22 Author : Neil
23 Data : 2005-4
24 ----------------------------------------------------------------------------------------------------------
25 This routine used for delay
26
27 *********************************************************************************************************/
28 void DELAY (int i)
29 {
30 1 int m;
31 1 for (m=0;m<i;m++)
32 1 ;
33 1 }
34
35
36
37 /*********************************************************************************************************
38 ----------------------------------------------------------------------------------------------------------
39 void SMBUS_ISR (void)
40 Author : Neil
41 Data : 2005-4
42 ----------------------------------------------------------------------------------------------------------
43 SMBus interrupt service routine:
44
45 *********************************************************************************************************/
46
47 void SMBUS_ISR (void) interrupt 7
48 {
49 1 switch (SMB0STA){ // Status code for the SMBus (SMB0STA register)
50 2
51 2 // Master Transmitter/Receiver: START condition transmitted.
52 2 // The R/W bit of the COMMAND word sent after this state will
53 2 // always be a zero (W) because for both read and write,
C51 COMPILER V7.06 CONTROL 06/13/2005 12:55:38 PAGE 2
54 2 // the memory address must be written first.
55 2 case SMB_START:
56 2 SMB0DAT = (COMMAND & 0xFE); // Load address of the slave to be accessed.
57 2 STA = 0; // Manually clear START bit
58 2 break;
59 2
60 2 // Master Transmitter/Receiver: Repeated START condition transmitted.
61 2 // This state should only occur during a read, after the memory address has been
62 2 // sent and acknowledged.
63 2 case SMB_RP_START:
64 2 SMB0DAT = COMMAND; // COMMAND should hold slave address + R.
65 2 STA = 0;
66 2 break;
67 2
68 2 // Master Transmitter: Slave address + WRITE transmitted. ACK received.
69 2 case SMB_MTADDACK:
70 2 SMB0DAT = HIGH_ADD; // Load high byte of memory address
71 2 // to be written.
72 2 break;
73 2
74 2 // Master Transmitter: Slave address + WRITE transmitted. NACK received.
75 2 // The slave is not responding. Send a STOP followed by a START to try again.
76 2 case SMB_MTADDNACK:
77 2 STO = 1;
78 2 STA = 1;
79 2 break;
80 2
81 2 // Master Transmitter: Data byte transmitted. ACK received.
82 2 // This state is used in both READ and WRITE operations. Check BYTE_NUMBER
83 2 // for memory address status - if only HIGH_ADD has been sent, load LOW_ADD.
84 2 // If LOW_ADD has been sent, check COMMAND for R/W value to determine
85 2 // next state.
86 2 case SMB_MTDBACK:
87 2 switch (BYTE_NUMBER){
88 3 case 2: // If BYTE_NUMBER=2, only HIGH_ADD
89 3 SMB0DAT = LOW_ADD; // has been sent.
90 3 BYTE_NUMBER--; // Decrement for next time around.
91 3 break;
92 3 case 1: // If BYTE_NUMBER=1, LOW_ADD was just sent.
93 3 if (COMMAND & 0x01){ // If R/W=READ, sent repeated START.
94 4 STO = 0;
95 4 STA = 1;
96 4
97 4 } else {
98 4 SMB0DAT = WORD; // If R/W=WRITE, load byte to write.
99 4 BYTE_NUMBER--;
100 4 }
101 3 break;
102 3 default: // If BYTE_NUMBER=0, transfer is finished.
103 3 STO = 1;
104 3 SM_BUSY = 0; // Free SMBus
105 3 }
106 2 break;
107 2
108 2
109 2 // Master Transmitter: Data byte transmitted. NACK received.
110 2 // Slave not responding. Send STOP followed by START to try again.
111 2 case SMB_MTDBNACK:
112 2 STO = 1;
113 2 STA = 1;
114 2 break;
115 2
C51 COMPILER V7.06 CONTROL 06/13/2005 12:55:38 PAGE 3
116 2 // Master Transmitter: Arbitration lost.
117 2 // Should not occur. If so, restart transfer.
118 2 case SMB_MTARBLOST:
119 2 STO = 1;
120 2 STA = 1;
121 2 break;
122 2
123 2 // Master Receiver: Slave address + READ transmitted. ACK received.
124 2 // Set to transmit NACK after next transfer since it will be the last (only)
125 2 // byte.
126 2 case SMB_MRADDACK:
127 2 AA = 0; // NACK sent on acknowledge cycle.
128 2 break;
129 2
130 2 // Master Receiver: Slave address + READ transmitted. NACK received.
131 2 // Slave not responding. Send repeated start to try again.
132 2 case SMB_MRADDNACK:
133 2 STO = 0;
134 2 STA = 1;
135 2 break;
136 2
137 2 // Data byte received. ACK transmitted.
138 2 // State should not occur because AA is set to zero in previous state.
139 2 // Send STOP if state does occur.
140 2 case SMB_MRDBACK:
141 2 STO = 1;
142 2 SM_BUSY = 0;
143 2 break;
144 2
145 2 // Data byte received. NACK transmitted.
146 2 // Read operation has completed. Read data register and send STOP.
147 2 case SMB_MRDBNACK:
148 2 WORD = SMB0DAT;
149 2 STO = 1;
150 2 SM_BUSY = 0; // Free SMBus
151 2 break;
152 2
153 2 // All other status codes meaningless in this application. Reset communication.
154 2 default:
155 2 STO = 1; // Reset communication.
156 2 SM_BUSY = 0;
157 2 break;
158 2 }
159 1
160 1 SI=0; // clear interrupt flag
161 1 }
162
163
164
165 /*********************************************************************************************************
166 ----------------------------------------------------------------------------------------------------------
167 void SM_Send (unsigned char , unsigned int , unsigned char )
168 Author : Neil
169 Data : 2005-4
170 ----------------------------------------------------------------------------------------------------------
171 SMBus byte write function-----------------------------------------------------
172 Writes a single byte at the specified memory location.
173
174 out_byte = data byte to be written
175 byte_address = memory location to be written into (2 bytes)
176 chip_address = device address of EEPROM chip to be written to
177
C51 COMPILER V7.06 CONTROL 06/13/2005 12:55:38 PAGE 4
178 *********************************************************************************************************/
179 void SM_Send (unsigned char chip_address, unsigned int byte_address, unsigned char out_byte)
180 {
181 1 while (SM_BUSY); // Wait for SMBus to be free.
182 1 SM_BUSY = 1; // Occupy SMBus (set to busy)
183 1 SMB0CN = 0x44; // SMBus enabled,
184 1 // ACK on acknowledge cycle
185 1
186 1 BYTE_NUMBER = 2; // 2 address bytes.
187 1 COMMAND = (chip_address | WRITE); // Chip select + WRITE
188 1
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -