📄 c8051f020.lst
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129 sfr PCA0L = 0xE9; /* PCA 0 TIMER - LOW BYTE */
130 sfr PCA0CPL0 = 0xEA; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - LOW BYTE */
131 sfr PCA0CPL1 = 0xEB; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - LOW BYTE */
132 sfr PCA0CPL2 = 0xEC; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - LOW BYTE */
133 sfr PCA0CPL3 = 0xED; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - LOW BYTE */
134 sfr PCA0CPL4 = 0xEE; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - LOW BYTE */
135 sfr RSTSRC = 0xEF; /* RESET SOURCE */
136 sfr B = 0xF0; /* B REGISTER */
137 sfr SCON1 = 0xF1; /* SERIAL PORT 1 CONTROL */
138 sfr SBUF1 = 0xF2; /* SERAIL PORT 1 DATA */
139 sfr SADDR1 = 0xF3; /* SERAIL PORT 1 */
140 sfr TL4 = 0xF4; /* TIMER 4 DATA - LOW BYTE */
141 sfr TH4 = 0xF5; /* TIMER 4 DATA - HIGH BYTE */
142 sfr EIP1 = 0xF6; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
143 sfr EIP2 = 0xF7; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
144 sfr SPI0CN = 0xF8; /* SERIAL PERIPHERAL INTERFACE 0 CONTROL */
145 sfr PCA0H = 0xF9; /* PCA 0 TIMER - HIGH BYTE */
146 sfr PCA0CPH0 = 0xFA; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - HIGH BYTE */
147 sfr PCA0CPH1 = 0xFB; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - HIGH BYTE */
148 sfr PCA0CPH2 = 0xFC; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - HIGH BYTE */
149 sfr PCA0CPH3 = 0xFD; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - HIGH BYTE */
150 sfr PCA0CPH4 = 0xFE; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - HIGH BYTE */
151 sfr WDTCN = 0xFF; /* WATCHDOG TIMER CONTROL */
152
153
154 /* BIT Registers */
155
156 /* TCON 0x88 */
157 sbit TF1 = TCON ^ 7; /* TIMER 1 OVERFLOW FLAG */
158 sbit TR1 = TCON ^ 6; /* TIMER 1 ON/OFF CONTROL */
159 sbit TF0 = TCON ^ 5; /* TIMER 0 OVERFLOW FLAG */
160 sbit TR0 = TCON ^ 4; /* TIMER 0 ON/OFF CONTROL */
161 sbit IE1 = TCON ^ 3; /* EXT. INTERRUPT 1 EDGE FLAG */
162 sbit IT1 = TCON ^ 2; /* EXT. INTERRUPT 1 TYPE */
163 sbit IE0 = TCON ^ 1; /* EXT. INTERRUPT 0 EDGE FLAG */
164 sbit IT0 = TCON ^ 0; /* EXT. INTERRUPT 0 TYPE */
165
166 /* SCON0 0x98 */
167 sbit SM00 = SCON0 ^ 7; /* SERIAL MODE CONTROL BIT 0 */
168 sbit SM10 = SCON0 ^ 6; /* SERIAL MODE CONTROL BIT 1 */
169 sbit SM20 = SCON0 ^ 5; /* MULTIPROCESSOR COMMUNICATION ENABLE */
170 sbit REN0 = SCON0 ^ 4; /* RECEIVE ENABLE */
171 sbit TB80 = SCON0 ^ 3; /* TRANSMIT BIT 8 */
172 sbit RB80 = SCON0 ^ 2; /* RECEIVE BIT 8 */
173 sbit TI0 = SCON0 ^ 1; /* TRANSMIT INTERRUPT FLAG */
174 sbit RI0 = SCON0 ^ 0; /* RECEIVE INTERRUPT FLAG */
175
176 /* IE 0xA8 */
177 sbit EA = IE ^ 7; /* GLOBAL INTERRUPT ENABLE */
178 sbit ET2 = IE ^ 5; /* TIMER 2 INTERRUPT ENABLE */
179 sbit ES0 = IE ^ 4; /* UART0 INTERRUPT ENABLE */
C51 COMPILER V7.06 C8051F020 04/19/2005 14:32:42 PAGE 4
180 sbit ET1 = IE ^ 3; /* TIMER 1 INTERRUPT ENABLE */
181 sbit EX1 = IE ^ 2; /* EXTERNAL INTERRUPT 1 ENABLE */
182 sbit ET0 = IE ^ 1; /* TIMER 0 INTERRUPT ENABLE */
183 sbit EX0 = IE ^ 0; /* EXTERNAL INTERRUPT 0 ENABLE */
184
185 /* IP 0xB8 */
186 sbit PT2 = IP ^ 5; /* TIMER 2 PRIORITY */
187 sbit PS = IP ^ 4; /* SERIAL PORT PRIORITY */
188 sbit PT1 = IP ^ 3; /* TIMER 1 PRIORITY */
189 sbit PX1 = IP ^ 2; /* EXTERNAL INTERRUPT 1 PRIORITY */
190 sbit PT0 = IP ^ 1; /* TIMER 0 PRIORITY */
191 sbit PX0 = IP ^ 0; /* EXTERNAL INTERRUPT 0 PRIORITY */
192
193 /* SMB0CN 0xC0 */
194 sbit BUSY = SMB0CN ^ 7; /* SMBUS 0 BUSY */
195 sbit ENSMB = SMB0CN ^ 6; /* SMBUS 0 ENABLE */
196 sbit STA = SMB0CN ^ 5; /* SMBUS 0 START FLAG */
197 sbit STO = SMB0CN ^ 4; /* SMBUS 0 STOP FLAG */
198 sbit SI = SMB0CN ^ 3; /* SMBUS 0 INTERRUPT PENDING FLAG */
199 sbit AA = SMB0CN ^ 2; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */
200 sbit SMBFTE = SMB0CN ^ 1; /* SMBUS 0 FREE TIMER ENABLE */
201 sbit SMBTOE = SMB0CN ^ 0; /* SMBUS 0 TIMEOUT ENABLE */
202
203 /* T2CON 0xC8 */
204 sbit TF2 = T2CON ^ 7; /* TIMER 2 OVERFLOW FLAG */
205 sbit EXF2 = T2CON ^ 6; /* EXTERNAL FLAG */
206 sbit RCLK0 = T2CON ^ 5; /* UART0 RX CLOCK SOURCE */
207 sbit TCLK0 = T2CON ^ 4; /* UART0 TX CLOCK SOURCE */
208 sbit EXEN2 = T2CON ^ 3; /* TIMER 2 EXTERNAL ENABLE FLAG */
209 sbit TR2 = T2CON ^ 2; /* TIMER 2 ON/OFF CONTROL */
210 sbit CT2 = T2CON ^ 1; /* TIMER OR COUNTER SELECT */
211 sbit CPRL2 = T2CON ^ 0; /* CAPTURE OR RELOAD SELECT */
212
213 /* PSW */
214 sbit CY = PSW ^ 7; /* CARRY FLAG */
215 sbit AC = PSW ^ 6; /* AUXILIARY CARRY FLAG */
216 sbit F0 = PSW ^ 5; /* USER FLAG 0 */
217 sbit RS1 = PSW ^ 4; /* REGISTER BANK SELECT 1 */
218 sbit RS0 = PSW ^ 3; /* REGISTER BANK SELECT 0 */
219 sbit OV = PSW ^ 2; /* OVERFLOW FLAG */
220 sbit F1 = PSW ^ 1; /* USER FLAG 1 */
221 sbit P = PSW ^ 0; /* ACCUMULATOR PARITY FLAG */
222
223 /* PCA0CN D8H */
224 sbit CF = PCA0CN ^ 7; /* PCA 0 COUNTER OVERFLOW FLAG */
225 sbit CR = PCA0CN ^ 6; /* PCA 0 COUNTER RUN CONTROL BIT */
226 sbit CCF4 = PCA0CN ^ 4; /* PCA 0 MODULE 4 INTERRUPT FLAG */
227 sbit CCF3 = PCA0CN ^ 3; /* PCA 0 MODULE 3 INTERRUPT FLAG */
228 sbit CCF2 = PCA0CN ^ 2; /* PCA 0 MODULE 2 INTERRUPT FLAG */
229 sbit CCF1 = PCA0CN ^ 1; /* PCA 0 MODULE 1 INTERRUPT FLAG */
230 sbit CCF0 = PCA0CN ^ 0; /* PCA 0 MODULE 0 INTERRUPT FLAG */
231
232 /* ADC0CN E8H */
233 sbit AD0EN = ADC0CN ^ 7; /* ADC 0 ENABLE */
234 sbit AD0TM = ADC0CN ^ 6; /* ADC 0 TRACK MODE */
235 sbit AD0INT = ADC0CN ^ 5; /* ADC 0 CONVERISION COMPLETE INTERRUPT FLAG */
236 sbit AD0BUSY = ADC0CN ^ 4; /* ADC 0 BUSY FLAG */
237 sbit AD0CM1 = ADC0CN ^ 3; /* ADC 0 START OF CONVERSION MODE BIT 1 */
238 sbit AD0CM0 = ADC0CN ^ 2; /* ADC 0 START OF CONVERSION MODE BIT 0 */
239 sbit AD0WINT = ADC0CN ^ 1; /* ADC 0 WINDOW COMPARE INTERRUPT FLAG */
240 sbit AD0LJST = ADC0CN ^ 0; /* ADC 0 RIGHT JUSTIFY DATA BIT */
241
C51 COMPILER V7.06 C8051F020 04/19/2005 14:32:42 PAGE 5
242 /* SPI0CN F8H */
243 sbit SPIF = SPI0CN ^ 7; /* SPI 0 INTERRUPT FLAG */
244 sbit WCOL = SPI0CN ^ 6; /* SPI 0 WRITE COLLISION FLAG */
245 sbit MODF = SPI0CN ^ 5; /* SPI 0 MODE FAULT FLAG */
246 sbit RXOVRN = SPI0CN ^ 4; /* SPI 0 RX OVERRUN FLAG */
247 sbit TXBSY = SPI0CN ^ 3; /* SPI 0 TX BUSY FLAG */
248 sbit SLVSEL = SPI0CN ^ 2; /* SPI 0 SLAVE SELECT */
249 sbit MSTEN = SPI0CN ^ 1; /* SPI 0 MASTER ENABLE */
250 sbit SPIEN = SPI0CN ^ 0; /* SPI 0 SPI ENABLE */
MODULE INFORMATION: STATIC OVERLAYABLE
CODE SIZE = ---- ----
CONSTANT SIZE = ---- ----
XDATA SIZE = ---- ----
PDATA SIZE = ---- ----
DATA SIZE = ---- ----
IDATA SIZE = ---- ----
BIT SIZE = ---- ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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