freq.s

Windows CE 6.0 针对PXA270的开发板的BSP参考代码

;
; Copyright (c) Microsoft Corporation.  All rights reserved.
;
;
; Use of this sample source code is subject to the terms of the Microsoft
; license agreement under which you licensed this sample source code. If
; you did not accept the terms of the license agreement, you are not
; authorized to use this sample source code. For the terms of the license,
; please see the license agreement between you and Microsoft or, if applicable,
; see the LICENSE.RTF on your install media or the root of your tools installation.
; THE SAMPLE SOURCE CODE IS PROVIDED "AS IS", WITH NO WARRANTIES.
;
;------------------------------------------------------------------------------
;
;   File:  freq.s
;
;   Kernel startup routine for the Intel Mainstone II board.
;
;------------------------------------------------------------------------------

    INCLUDE kxarm.h
    INCLUDE mainstoneii.inc
    INCLUDE xlli_bulverde_defs.inc

    IMPORT xlli_GPIO_init
    IMPORT xlli_setClocks
    IMPORT xlli_freq_change
    
    TEXTAREA

;-------------------------------------------------------------------------------
;
; OALXScaleSetFrequencies: Configures the Bulverde core and memory clock
;                          frequencies.
;
; Inputs: None.
; 
; On return: N/A.
;
; Register used: r9
;
;-------------------------------------------------------------------------------
;
    ALIGN
    NESTED_ENTRY OALXScaleSetFrequencies
    ; TODO - we don't have a stack yet, but need to save the caller's return address...
    mov r9, lr
    PROLOG_END

    bl      xlli_GPIO_init 

    ; Route the 32768 Hz Oscillator to the RTC, and provide for
    ; trimming the accuracy of that crystal.

    ldr	r1, =xlli_CLKREGS_PHYSICAL_BASE    ; OSCC = OON | TOUT
    mov	r2, #(xlli_OSCC_OON :OR: xlli_OSCC_TOUT_EN)
    str	r2, [r1, #xlli_OSCC_offset]

    ; Trim the RTC accuracy. If it uses the 13 MHz clock as the reference
    ; frequency, this is required since it divides down by 400 to 32500,
    ; not 32768.
    ; If it uses the actual watch crystal, it should be 32768 +- the error,
    ; and may or may not be required. The error could be due to the uncalibrated 
    ; watch crystal or the parasitic capacitance inherent in the board layout.
    ; Some empirical timing over an hour on a mainstone did not reveal any
    ; error. Hence leaving the crystal freq. to its original value 32768 Hz.
    ; Uncomment the code below and set ACTUAL_CRYSTAL_FREQ if the measured
    ; frequency is different from 32.768 kHz.
    
;ACTUAL_CRYSTAL_FREQ	EQU	32768	; Measured frequency may or may not be 32768

;    ldr	r1, =xlli_RTCREGS_PHYSICAL_BASE
;    ldr	r2, =ACTUAL_CRYSTAL_FREQ - 1            ; Load the crystals actual frequency - 1
;    str	r2, [r1, #xlli_RTTR_offset]             ; Store this in the RTC Trim Register

    bl      xlli_setClocks

    bl      xlli_freq_change

    ; Do Mainstone-Specific Board Initialization
    ;
    ldr     r2,  =MAINSTONEII_BASE_REG_PA_FPGA

    ; setup MISC_WR1,2 to their initial states
    ;
    ldr     r1, =MISCWR1_VAL
    str     r1, [r2, #MISCWR1_OFFSET]

    ldr     r1, =MISCWR2_VAL
    str     r1, [r2, #MISCWR2_OFFSET] 
    
    mov     lr, r9
    
  IF Interworking :LOR: Thumbing
    bx  lr
  ELSE
    mov  pc, lr          ; return
  ENDIF
 
    ENTRY_END
    
    END 

;------------------------------------------------------------------------------