intr_fpga.h

Windows CE 6.0 针对PXA270的开发板的BSP参考代码

//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this sample source code is subject to the terms of the Microsoft
// license agreement under which you licensed this sample source code. If
// you did not accept the terms of the license agreement, you are not
// authorized to use this sample source code. For the terms of the license,
// please see the license agreement between you and Microsoft or, if applicable,
// see the LICENSE.RTF on your install media or the root of your tools installation.
// THE SAMPLE SOURCE CODE IS PROVIDED "AS IS", WITH NO WARRANTIES.
//
//------------------------------------------------------------------------------
//
//  File: intr_fpga.h
//
//  This header file defines values for working with the 
//  FPGA interrupt controller.
//
#ifndef __INTR_FPGA_H
#define __INTR_FPGA_H

//------------------------------------------------------------------------------

#define INTMSK_RESERVED_BITS          0xFFFF1100
#define INTSETCLR_RESERVED_BITS       0xFFFF1100

#define IRQ_GPIO0_PCMCIA_S1           (IRQ_BULVERDE_MAX + 16)  // 79, 0x4F
#define IRQ_GPIO0_PCMCIA_S1_CSC       (IRQ_BULVERDE_MAX + 15)  // 78, 0x4E
#define IRQ_GPIO0_PCMCIA_S1_CD        (IRQ_BULVERDE_MAX + 14)  // 77, 0x4D
#define IRQ_GPIO0_RSVD2               (IRQ_BULVERDE_MAX + 13)  // 76  ** RESERVED **
#define IRQ_GPIO0_PCMCIA_S0           (IRQ_BULVERDE_MAX + 12)  // 75, 0x4B
#define IRQ_GPIO0_PCMCIA_S0_CSC       (IRQ_BULVERDE_MAX + 11)  // 74, 0x4A
#define IRQ_GPIO0_PCMCIA_S0_CD        (IRQ_BULVERDE_MAX + 10)  // 73, 0x49
#define IRQ_GPIO0_RSVD1               (IRQ_BULVERDE_MAX + 9)   // 72  ** RESERVED **
#define IRQ_GPIO0_EXPBD               (IRQ_BULVERDE_MAX + 8)   // 71, 0x47
#define IRQ_GPIO0_MSINS               (IRQ_BULVERDE_MAX + 7)   // 70, 0x46
#define IRQ_GPIO0_PENIRQ              (IRQ_BULVERDE_MAX + 6)   // 69, 0x45
#define IRQ_GPIO0_UCB1400             (IRQ_BULVERDE_MAX + 5)   // 68, 0x44
#define IRQ_GPIO0_ETHERNET            (IRQ_BULVERDE_MAX + 4)   // 67, 0x43
#define IRQ_GPIO0_USBCD               (IRQ_BULVERDE_MAX + 3)   // 66, 0x42
#define IRQ_GPIO0_USIMCD              (IRQ_BULVERDE_MAX + 2)   // 65, 0x41
#define IRQ_GPIO0_MMCCD               (IRQ_BULVERDE_MAX + 1)   // 64, 0x40

#define IRQ_MAINSTONEII_GPIO0_MIN     IRQ_GPIO0_MMCCD
#define IRQ_MAINSTONEII_GPIO0_MAX     IRQ_GPIO0_PCMCIA_S1

#define FPGA_INT_BIT(n)              (1 << (n - IRQ_MAINSTONEII_GPIO0_MIN))

//------------------------------------------------------------------------------

#endif