types.h

linux上实现的多种型号的AVR模拟器

#include <inttypes.h>

#define UNPROGRAMMED 0
#define PROGRAMMED 1

/* return port address */
#define IO_ADDRESS(port) io_port[index_ports[port]].address
#define ISPORT(port) (index_ports[port]!=-1)
#define ISFLAG(flag) (index_flags[flag]!=-1)
#define ISPIN(pin)  (index_pins[pin]!=-1)

/* structure of AVR command */
typedef struct {
  char mnemocode[16]; 
  int code;
  int mask;
  unsigned char num_words;
  int (*arg1)(char *mnemocode,int command,int address);
  int (*arg2)(char *mnemocode,int command,int address);
  void (*command)(void);
} Command;

/* structure of listing */
typedef struct {
  char mnemocode[20];
  char comment[6];
  void (*function_command)(void);
  int arg1,arg2;
  int flags;
  int number_line;
  int code;
  unsigned char num_words;
} ListCommand;

/* I/O ports */
typedef struct {
  int code,address,write_mask,read_mask,init_value;
} IO_port;

enum{LOW,HIGH};
/* 16-bit I/O ports */
typedef struct {
  int code,type;
  uint8_t *temp;
} IO_port16;

/* structure of pin's definition */
typedef struct {
  int code,data_address,pins_address,mask;
} Pin;

/* used in load and save ports functions */
typedef struct {
  int data,direct,pins;
} Ports;

/* structure of flag mask */
typedef struct {
  int flag_code,port_code,flag_mask;
} Flag;

/* structure of microcontrollers */
typedef struct {
  char *name;
  int size_gpr,size_io_reg,size_sram;
  int size_flash; /* size in words*/
  int size_eeprom;
  int *interrupts;
  IO_port *io_registers;
  Pin *pins;
  Flag *flags;
} Microcontroller;

/* definition of I/O ports */
typedef struct {
  char *name;
  char *fullname;
} Descr_io_port;

/* definition of button */
typedef struct {
  char *name;                 /* Label                          */
  void (*callback)();         /* callback function              */
  void *call_data;            /* call_data                      */
  char *name_pixmap;          /* filename of pixmap             */
  char *prompt_str;           /* */
  Widget widget;
  Pixmap pixmap;
} Buttons;

/* The following structure is used for menu construction */
#define BUTTON    0
#define CHECK     1
#define RADIO     2 
#define SEPARATOR 3
typedef struct _Menu{
  int     type;
  char    *name;          /* Used as the menu item name             */
  char    *mnemonic;      /* If non-null Use first char as mnemonic */
  char    *accelerator_text;
  char    *accelerator;   /* An accelerator                         */
  struct _Menu  *sub_menu;/* sub menu                               */
  int     n_sub_items;
  void    (*callback)();  /* Function to call when selected         */
  void    *data;          /* Call data for callback function        */
  Widget  button;
  Widget  pulldown;
} Menu;

/* struct of scroll window */
typedef struct {
  Widget draw;
  Widget v_scrb;
  int font_width,font_height;
  GC gc;
  int num_commands,current_line_deb;
  Dimension height,width;
  int *display_lines;     /* address of command */
  Pixel background,foreground;
} DrawArea;

/* widgets of port_window */
typedef struct{
  Widget button1,data,button2;
} Line_port_window;

/* widget's data of port_window */
typedef struct{
  char state;
  char *filename;
  FILE *file;
} Data_port_window;

typedef struct{
  Widget draw,vscr_bar,label_widget,address_widget,data_widget,chars_widget,
    address_text_widget,data_type_widget;
  Dimension height,width;
  Pixmap label,address,data,chars;
  GC gc,gc_new,label_gc,address_gc,data_gc,chars_gc;
  int font_width,font_height;
  Window window,label_window,address_window,data_window,chars_window;
  int num_lines,cur_line,max_lines;
  uint8_t *pdata;          /* data to display */
  int data_size;           /* size of date */
  int data_type;           /* HEX or DEC */
  int memory_type;
  Pixel label_bg,address_bg,data_bg,chars_bg;
  uint8_t *mem_changed;
  uint32_t mem_offset;
} MemoryWindowDrawArea;

enum{HEX,DEC};
/* memory's types */
enum{M_REGISTERS,M_IO_REGISTERS,M_EX_IO_REGISTERS,M_SRAM,M_DATA,M_EEPROM};

/* fast button */
#define LOAD        0
#define RELOAD      1
#define TRACE_INTO  3
#define STEP_OVER   4
#define STEP_OUT    5
#define MULTI_STEP  6 
#define AUTO_STEP   7
#define RUN         9
#define STOP        10
#define RESET_      12

#define FILE_MENU      0
#define MEMORY_MENU    1
#define DEBUG_MENU     2
#define OPTIONS_MENU   3
#define HELP_MENU      4

#define GPR_BUTTON     0
#define IO_BUTTON      1
#define SRAM_BUTTON    2
#define EEPROM_BUTTON  3
#define MEMORY_BUTTON  4

#define RESET_BUTTON   0
#define RUN_BUTTON     1
#define STOP_BUTTON    2
#define TRACE_INTO_BUTTON 3
#define STEP_OVER_BUTTON  4
#define STEP_OUT_BUTTON   5
#define MULTI_STEP_BUTTON 6
#define AUTO_STEP_BUTTON  7

#define HEX 0 /* hec data */
#define DEC 1 /* decimal data */

#define uS  0
#define mS  1
#define S   2

#define BREAKPOINT 1
#define FLASH 0
#define EEPROM 1

/* debugger's flags */
#define DEBUG_INTERRUPT 1

/* interrupts definition */

enum{
  RESET,           /* Hardware Pin,Power-on Reset and Watchdog Reset */
    INT0,            /* External Interrupt Request 0      */
    INT1,            /* External Interrupt Request 1      */
    INT2,            /* External Interrupt Request 2      */
    INT3,            /* External Interrupt Request 3      */
    INT4,            /* External Interrupt Request 4      */
    INT5,            /* External Interrupt Request 5      */
    INT6,            /* External Interrupt Request 6      */
    INT7,            /* External Interrupt Request 7      */
    PCINT0,          /* Pin Change Interrupt Request 0    */
    PCINT1,          /* Pin Change Interrupt Request 1    */
    TIMER3_CAPT,     /* Timer/Counter3 Capture Event      */
    TIMER3_COMPA,    /* Timer/Counter3 Campare Match A    */
    TIMER3_COMPB,    /* Timer/Counter3 Campare Match B    */
    TIMER3_COMPC,    /* Timer/Counter3 Campare Match C    */
    TIMER3_OVF,      /* Timer/Counter3 Overflow           */
    TIMER2_COMP,     /* Timer/Counter2 Campare Match      */
    TIMER2_OVF,      /* Timer/Counter2 Overflow           */
    TIMER1_CAPT,     /* Timer/Counter1 Capture Event      */
    TIMER1_COMPA,    /* Timer/Counter1 Campare Match A    */
    TIMER1_COMPB,    /* Timer/Counter1 Campare Match B    */
    TIMER1_COMPC,    /* Timer/Counter1 Campare Match C    */
    TIMER1_OVF,      /* Timer/Counter1 Overflow           */
    TIMER0_COMP,     /* Timer/Counter0 Campare Match      */
    TIMER0_OVF,      /* Timer/Counter0 Overflow           */
    SPI_STC,         /* SPI Serial Transfer Complete      */
    UART0_RX,        /* UART0, RX Complete                */
    UART0_UDRE,      /* UART0, Data Register Empty        */
    UART0_TX,        /* UART0, TX Complete                */
    UART1_RX,        /* UART1, RX Complete                */
    UART1_UDRE,      /* UART1, Data Register Empty        */
    UART1_TX,        /* UART1, TX Complete                */
    ADC,             /* ADC Conversion Complete           */
    EE_READY,        /* EEPROM Ready                      */
    ANALOG_COMP,     /* Analog Comparator                 */
    TWSI,            /* 2-wire Serial Interface           */
    SPM_RDY,         /* Store Program Memory Ready        */
    MAX_CODE_INT
    };
    

/* definition of I/O ports */
enum{ 
  UBRR1L=0,       /* UART1 Baud Rate Register Low      */
    UBRR1H,       /* UART1 Baud Rate Register High     */
    UCSR1C,       /* UART1 Control Register and Status Register */
    UCSR1B,       /* UART1 Control Register            */
    UCSR1A,       /* UART1 Status Register             */
    UDR1,         /* UART1 I/O Data Register Low       */
    UBRR0L,       /* UART0 Baud Rate Register          */
    UBRR0H,       /* UART0 Baud Register High          */
    UCSR0C,       /* UART0 Control Register and Status Register */
    UCSR0B,       /* UART0 Control Register            */
    UCSR0A,       /* UART0 Status Register             */
    UDR0,         /* UART0 I/O Data Register           */
    UBRRHI,       /* UART Baud Register High           */

    PING,         /* Input Pins, Port G                */
    DDRG,         /* Data Direction Register, Port G   */
    PORTG,        /* Data Register, Port G             */
    PINF,         /* Input Pins, Port F                */
    DDRF,         /* Data Direction Register, Port F   */
    PORTF,        /* Data Register, Port F             */
    PINE,         /* Input Pins, Port E                */
    DDRE,         /* Data Direction Register, Port E   */
    PORTE,        /* Data Register, Port E             */
    PIND,         /* Input Pins, Port D                */
    DDRD,         /* Data Direction Register, Port D   */
    PORTD,        /* Data Register, Port D             */
    PINC,         /* Input Pins, Port C                */
    DDRC,         /* Data Direction Register, Port C   */
    PORTC,        /* Data Register, Port C             */
    PINB,         /* Input Pins, Port B                */
    DDRB,         /* Data Direction Register, Port B   */
    PORTB,        /* Data Register, Port B             */
    PINA,         /* Input Pins, Port A                */
    DDRA,         /* Data Direction Register, Port A   */
    PORTA,        /* Data Register, Port A             */
    
    ACSR,         /* Analog Comparator Control and Status Register */
   
    SPCR,         /* SPI Control Register              */
    SPSR,         /* SPI Status Register               */
    SPDR,         /* SPI I/O Data Register             */
   
    EECR,         /* EEPROM Control Register           */
    EEDR,         /* EEPROM Data Register              */
    EEARL,        /* EEPROM Address Register Low       */
    EEARH,        /* EEPROM Address Register High      */

    WDTCR,        /* Watchdog Timer Control Register   */

    ICR3L,        /* Timer/Counter3 Input Capture Register Low Byte */
    ICR3H,        /* Timer/Counter3 Input Capture Register High Byte */
    OCR3CL,       /* Timer/Counter3 Output Capture RegisterC Low Byte */
    OCR3CH,       /* Timer/Counter3 Output Capture RegisterC High Byte */
    OCR3BL,       /* Timer/Counter3 Output Capture RegisterB Low Byte */
    OCR3BH,       /* Timer/Counter3 Output Capture RegisterB High Byte */
    OCR3AL,       /* Timer/Counter3 Output Capture RegisterA Low Byte */
    OCR3AH,       /* Timer/Counter3 Output Capture RegisterA High Byte */
    TCNT3L,       /* Timer/Counter3 Low Byte                */
    TCNT3H,       /* Timer/Counter3 High Byte               */
    TCCR3C,       /* Timer/Counter3 Control Register C      */
    TCCR3B,       /* Timer/Counter3 Control Register B      */
    TCCR3A,       /* Timer/Counter3 Control Register A      */
    OCR2,         /* Timer/Counter2 Output Compare Register */
    TCNT2,        /* Timer/Counter2 (8-bit)            */
    TCCR2,        /* Timer/Counter2 Control Register   */
    ICR1L,        /* Timer/Counter1 Input Capture Register Low Byte */
    ICR1H,        /* Timer/Counter1 Input Capture Register High Byte */
    OCR1CL,       /* Timer/Counter1 Output Capture RegisterC Low Byte */
    OCR1CH,       /* Timer/Counter1 Output Capture RegisterC High Byte */
    OCR1BL,       /* Timer/Counter1 Output Capture RegisterB Low Byte */
    OCR1BH,       /* Timer/Counter1 Output Capture RegisterB High Byte */
    OCR1AL,       /* Timer/Counter1 Output Capture RegisterA Low Byte */
    OCR1AH,       /* Timer/Counter1 Output Capture RegisterA High Byte */
    TCNT1L,       /* Timer/Counter1 Low Byte                */
    TCNT1H,       /* Timer/Counter1 High Byte               */
    TCCR1C,       /* Timer/Counter1 Control Register C      */
    TCCR1B,       /* Timer/Counter1 Control Register B      */
    TCCR1A,       /* Timer/Counter1 Control Register A      */
    OCR0,         /* Timer/Counter0 Output Compare Register */
    TCNT0,        /* Timer/Counter0 (8-bit)                 */
    TCCR0,        /* Timer/Counter0 Control Register        */
    ASSR,         /* Asynchronous mode Status Register      */
    SFIOR,        /* Special Function IO Register           */
    CLKPR,        /* Clock Prescale Register */

    MCUSR,        /* MCU general Status Regsiter            */
    MCUCR,        /* MCU general Control Regsiter           */
    EMCUCR,       /* Extended MCU general Control Register  */

    SPMCR,        /* Store Program Memory Control Register  */
    TIFR ,        /* Timer/Counter Interrupt Flag Register  */
    TIMSK,        /* Timer/Counter Interrupt Mask Register  */
    ETIMSK,       /* Extended Timer/Counter Interrupt Mask Register */
    ETIFR,        /* Extended Timer/Counter Interrupt Flag Register */
    GIFR,         /* General Interrupt Flag Register        */
    GIMSK,        /* General Interrupt Mask Register        */
    GICR,         /* General Interrupt Control Register     */
    PCMSK0,       /* Pin Change Mask Register 0             */
    PCMSK1,       /* Pin Change Mask Register 1             */
    SPL,          /* Stack Pointer Low                      */
    SPH,          /* Stack Pointer High                     */
    SREG,         /* Status Register                        */
    RAMPZ,        /* RAM Page Z Select Register             */
    XDIV,         /* XTAL Divide Control Register           */

    EICR,         /* External Interrupt Control Register    */
    EICRB,        /* External Interrupt Control Register B  */
    EICRA,        /* External Interrupt Control Register A  */
    EIMSK,        /* External Interrupt Mask Register       */
    EIFR,         /* External Interrupt Flag Register       */

    ADMUX,        /* ADC Multiplexer Select Register        */
    ADCSR,        /* ADC Control and Status Register        */
    ADCSRA,       /* ADC Control and Status Register A      */
    ADCH,         /* ADC Data Register High                 */
    ADCL,         /* ADC Data Register Low                  */

    TWCR,         /* 2-wire Serial Interface Control Register */
    TWDR,         /* 2-wire Serial Interface Data Register  */
    TWAR,         /* 2-wire Serial Interface (Slave) Address Register */
    TWSR,         /* 2-wire Serial Interface Status Register */
    TWBR,         /* 2-wire Serial Interface Bit Rate Register */

    OSCCAL,       /* Oscillator Calibration Register        */
    OCDR,         /* On-Chip Debug Related Register         */

    XMCRB,        /* External Memory Control Register B     */
    XMCRA,        /* External Memory Control Register A     */
    MAX_CODE_PORTS,
    };

/* Flags in SREG */
#define FLAG_C 1<<0
#define FLAG_Z 1<<1