atmega128.h

linux上实现的多种型号的AVR模拟器

int atmega128_int[]={
  RESET,INT0,INT1,INT2,INT3,INT4,INT5,INT6,INT7,TIMER2_COMP,TIMER2_OVF,
  TIMER1_CAPT,TIMER1_COMPA,TIMER1_COMPB,TIMER1_OVF,TIMER0_COMP,TIMER0_OVF,
  SPI_STC,UART0_RX,UART0_UDRE,UART0_TX,ADC,EE_READY,ANALOG_COMP,TIMER1_COMPC,
  TIMER3_CAPT,TIMER3_COMPA,TIMER3_COMPB,TIMER3_COMPC,TIMER3_OVF,UART1_RX,
  UART1_UDRE,UART1_TX,TWSI,SPM_RDY,-1};

IO_port atmega128_io[]={
  {UCSR1C,0x9D,0x7F,0x7F,0x06},
  {UDR1,  0x9C,0xFF,0xFF,0},
  {UCSR1A,0x9B,0x43,0xFF,0x20},
  {UCSR1B,0x9A,0xFD,0xFF,0},
  {UBRR1L,0x99,0xFF,0xFF,0},
  {UBRR1H,0x98,0x0F,0x0F,0},
  {UCSR0C,0x95,0x7F,0x7F,0x06},
  {UBRR0H,0x90,0x0F,0x0F,0},
  {TCCR3C,0x8C,0xE0,0x00,0},  
  {TCCR3A,0x8B,0xFF,0xFF,0},
  {TCCR3B,0x8A,0xDF,0xDF,0},
  {TCNT3H,0x89,0xFF,0xFF,0},
  {TCNT3L,0x88,0xFF,0xFF,0},
  {OCR3AH,0x87,0xFF,0xFF,0},
  {OCR3AL,0x86,0xFF,0xFF,0},
  {OCR3BH,0x85,0xFF,0xFF,0},
  {OCR3BL,0x84,0xFF,0xFF,0},
  {OCR3CH,0x83,0xFF,0xFF,0},
  {OCR3CL,0x82,0xFF,0xFF,0},
  {ICR3H, 0x81,0xFF,0xFF,0},
  {ICR3L, 0x80,0xFF,0xFF,0},
  {ETIMSK,0x7D,0x3F,0x3F,0},
  {ETIFR, 0x7C,0x3F,0x3F,0},
  {TCCR1C,0x7A,0xE0,0x00,0},
  {OCR1CH,0x79,0xFF,0xFF,0},
  {OCR1CL,0x78,0xFF,0xFF,0},
  {TWCR,  0x74,0xF5,0xFD,0},
  {TWDR,  0x73,0xFF,0xFF,0xFF},
  {TWAR,  0x72,0xFF,0xFF,0xFE},
  {TWSR,  0x71,0x03,0xFB,0xF8},
  {TWBR,  0x70,0xFF,0xFF,0},
  {OSCCAL,0x6F,0xFF,0xFF,0},
  {XMCRA, 0x6D,0x7E,0x7E,0},
  {XMCRB, 0x6C,0x87,0x87,0},
  {EICRA, 0x6A,0xFF,0xFF,0},
  {SPMCR, 0x68,0x9F,0xDF,0},
  {PORTG, 0x65,0x1F,0x1F,0},
  {DDRG,  0x64,0x1F,0x1F,0},
  {PING,  0x63,0x00,0x1F,0},
  {PORTF, 0x62,0xFF,0xFF,0},
  {DDRF,  0x61,0xFF,0xFF,0},
  {SREG,  0x3F,0xFF,0xFF,0},
  {SPH,   0x3E,0xFF,0xFF,0},
  {SPL,   0x3D,0xFF,0xFF,0},
  {XDIV,  0x3C,0xFF,0xFF,0},
  {RAMPZ, 0x3B,0x01,0x01,0},
  {EICRB, 0x3A,0xFF,0xFF,0},
  {EIMSK, 0x39,0xFF,0xFF,0},
  {EIFR,  0x38,0xFF,0xFF,0},
  {TIMSK, 0x37,0xFF,0xFF,0},
  {TIFR,  0x36,0xFF,0xFF,0},
  {MCUCR, 0x35,0xFF,0xFF,0},
  {MCUSR, 0x34,0x9F,0x9F,0},
  {TCCR0, 0x33,0xFF,0x7F,0},
  {TCNT0, 0x32,0xFF,0xFF,0},
  {OCR0,  0x31,0xFF,0xFF,0},
  {ASSR,  0x30,0x08,0x0F,0},
  {TCCR1A,0x2F,0xFF,0xFF,0},
  {TCCR1B,0x2E,0xDF,0xDF,0},
  {TCNT1H,0x2D,0xFF,0xFF,0},
  {TCNT1L,0x2C,0xFF,0xFF,0},
  {OCR1AH,0x2B,0xFF,0xFF,0},
  {OCR1AL,0x2A,0xFF,0xFF,0},
  {OCR1BH,0x29,0xFF,0xFF,0},
  {OCR1BL,0x28,0xFF,0xFF,0},
  {ICR1H, 0x27,0,0xFF,0},
  {ICR1L, 0x26,0,0xFF,0},
  {TCCR2, 0x25,0xFF,0x7F,0},
  {TCNT2, 0x24,0xFF,0xFF,0},
  {OCR2,  0x23,0xFF,0xFF,0},
  {OCDR,  0x22,0xFF,0xFF,0},
  {WDTCR, 0x21,0x1F,0x1F,0},
  {SFIOR, 0x20,0x9F,0x9F,0},
  {EEARH, 0x1F,0x0F,0x0F,0},
  {EEARL, 0x1E,0xFF,0xFF,0},
  {EEDR,  0x1D,0xFF,0xFF,0},
  {EECR,  0x1C,0x0F,0x0F,0},
  {PORTA, 0x1B,0xFF,0xFF,0},
  {DDRA,  0x1A,0xFF,0xFF,0},
  {PINA,  0x19,0x00,0xFF,0},
  {PORTB, 0x18,0xFF,0xFF,0},
  {DDRB,  0x17,0xFF,0xFF,0},
  {PINB,  0x16,0x00,0xFF,0},
  {PORTC, 0x15,0xFF,0xFF,0},
  {DDRC,  0x14,0xFF,0xFF,0},
  {PINC,  0x13,0x00,0xFF,0},
  {PORTD, 0x12,0xFF,0xFF,0},
  {DDRD,  0x11,0xFF,0xFF,0},
  {PIND,  0x10,0x00,0xFF,0},
  {SPDR,  0x0F,0xFF,0xFF,0},
  {SPSR,  0x0E,0x01,0xC1,0},
  {SPCR,  0x0D,0xFF,0xFF,0},
  {UDR0,  0x0C,0xFF,0xFF,0},
  {UCSR0A,0x0B,0x43,0xFF,0x20},
  {UCSR0B,0x0A,0xFD,0xFF,0},
  {UBRR0L,0x09,0xFF,0xFF,0},
  {ACSR,  0x08,0xDF,0xFF,0},
  {ADMUX, 0x07,0xFF,0xFF,0},
  {ADCSRA,0x06,0xFF,0xFF,0},
  {ADCH,  0x05,0x00,0xFF,0},
  {ADCL,  0x04,0x00,0xFF,0},
  {PORTE, 0x03,0xFF,0xFF,0},
  {DDRE,  0x02,0xFF,0xFF,0},
  {PINE,  0x01,0x00,0xFF,0},
  {PINF,  0x00,0x00,0xFF,0},
  {-1,0,0,0}
};

Pin atmega128_pins[]={
  {SS_PIN,  0x18,0x16,1<<0},
  {SCK_PIN, 0x18,0x16,1<<1},
  {MOSI_PIN,0x18,0x16,1<<2},
  {MISO_PIN,0x18,0x16,1<<3},
  {OC0_PIN, 0x18,0x16,1<<4},{PWM0_PIN, 0x18,0x16,1<<4},
  {OC1A_PIN,0x18,0x16,1<<5},
  {OC1B_PIN,0x18,0x16,1<<6},
  {OC2_PIN, 0x18,0x16,1<<7},{OC1C_PIN,0x18,0x16,1<<7},

  {INT0_PIN,0x12,0x10,1<<0},{SCL_PIN, 0x12,0x10,1<<0},
  {INT1_PIN,0x12,0x10,1<<1},{SDA_PIN, 0x12,0x10,1<<1},
  {INT2_PIN,0x12,0x10,1<<2},{RXD1_PIN,0x12,0x10,1<<2},
  {INT3_PIN,0x12,0x10,1<<3},{TXD1_PIN,0x12,0x10,1<<3},
  {IC1_PIN, 0x12,0x10,1<<4},
  {T0_PIN,  0x12,0x10,1<<6},
  {T1_PIN,  0x12,0x10,1<<7},

  {RXD0_PIN,0x03,0x01,1<<0},{PDI_PIN, 0x03,0x01,1<<0},
  {TXD0_PIN,0x03,0x01,1<<1},{PDO_PIN, 0x03,0x01,1<<1},
  {AIN0_PIN,0x03,0x01,1<<2},
  {AIN1_PIN,0x03,0x01,1<<3},{OC3A_PIN,0x03,0x01,1<<3},
  {INT0_PIN,0x03,0x01,1<<4},{OC3B_PIN,0x03,0x01,1<<4},
  {INT1_PIN,0x03,0x01,1<<5},{OC3C_PIN,0x03,0x01,1<<5},
  {INT2_PIN,0x03,0x01,1<<6},{T3_PIN,  0x03,0x01,1<<6},
  {INT3_PIN,0x03,0x01,1<<7},{IC3_PIN, 0x03,0x01,1<<7},

  {ADC0_PIN,0x62,0x00,1<<0},
  {ADC1_PIN,0x62,0x00,1<<1},
  {ADC2_PIN,0x62,0x00,1<<2},
  {ADC3_PIN,0x62,0x00,1<<3},
  {ADC4_PIN,0x62,0x00,1<<4},{TCK_PIN, 0x62,0x00,1<<4},
  {ADC5_PIN,0x62,0x00,1<<5},{TMS_PIN, 0x62,0x00,1<<5},
  {ADC6_PIN,0x62,0x00,1<<6},{TDO_PIN, 0x62,0x00,1<<6},
  {ADC7_PIN,0x62,0x00,1<<7},{TDI_PIN, 0x62,0x00,1<<7},

  {WR_PIN,  0x65,0x63,1<<0},
  {RD_PIN,  0x65,0x63,1<<1},
  {ALE_PIN, 0x65,0x63,1<<2},
  {TOSC2_PIN,0x65,0x63,1<<3},
  {TOSC1_PIN,0x65,0x63,1<<4},
  {-1,0,0,0}
};

Flag atmega128_flags[]={
  {UCPOL1_FLAG,UCSR1C,1<<0},
  {UCSZ10_FLAG,UCSR1C,1<<1},
  {UCSZ11_FLAG,UCSR1C,1<<2},
  {USBS1_FLAG, UCSR1C,1<<3},
  {UPM10_FLAG, UCSR1C,1<<4},
  {UPM11_FLAG, UCSR1C,1<<5},
  {UMSEL1_FLAG,UCSR1C,1<<6},

  {MPCM1_FLAG, UCSR1A,1<<0},
  {U2X1_FLAG,  UCSR1A,1<<1},
  {PE1_FLAG,   UCSR1A,1<<2},
  {DOR1_FLAG,  UCSR1A,1<<3},
  {FE1_FALG,   UCSR1A,1<<4},
  {UDRE1_FLAG, UCSR1A,1<<5},
  {TXC1_FLAG,  UCSR1A,1<<6},
  {RXC1_FLAG,  UCSR1A,1<<7},

  {TXB81_FLAG, UCSR1B,1<<0},
  {RXB81_FLAG, UCSR1B,1<<1},
  {UCSZ12_FLAG,UCSR1B,1<<2},
  {TXEN1_FLAG, UCSR1B,1<<3},
  {RXEN1_FLAG, UCSR1B,1<<4},
  {UDRIE1_FLAG,UCSR1B,1<<5},
  {TXCIE1_FLAG,UCSR1B,1<<6},
  {RXCIE1_FLAG,UCSR1B,1<<7},

  {UCPOL0_FLAG,UCSR0C,1<<0},
  {UCSZ00_FLAG,UCSR0C,1<<1},
  {UCSZ01_FLAG,UCSR0C,1<<2},
  {USBS0_FLAG, UCSR0C,1<<3},
  {UPM00_FLAG, UCSR0C,1<<4},
  {UPM01_FLAG, UCSR0C,1<<5},
  {UMSEL0_FLAG,UCSR0C,1<<6},

  {FOC3C_FLAG, TCCR3C,1<<5},
  {FOC3B_FLAG, TCCR3C,1<<6},
  {FOC3A_FLAG, TCCR3C,1<<7},

  {WGM30_FLAG, TCCR3A,1<<0},
  {WGM31_FLAG, TCCR3A,1<<1},
  {COM3C0_FLAG,TCCR3A,1<<2},
  {COM3C1_FLAG,TCCR3A,1<<3},
  {COM3B0_FLAG,TCCR3A,1<<4},
  {COM3B1_FLAG,TCCR3A,1<<5},
  {COM3A0_FLAG,TCCR3A,1<<6},
  {COM3A1_FLAG,TCCR3A,1<<7},

  {CS30_FLAG,  TCCR3B,1<<0},
  {CS31_FLAG,  TCCR3B,1<<1},
  {CS32_FLAG,  TCCR3B,1<<2},
  {WGM32_FLAG, TCCR3B,1<<3},
  {WGM33_FLAG, TCCR3B,1<<4},
  {ICES3_FLAG, TCCR3B,1<<6},
  {ICNC3_FLAG, TCCR3B,1<<7},

  {OCIE1C_FLAG,ETIMSK,1<<0},
  {OCIE3C_FLAG,ETIMSK,1<<1},
  {TOIE3_FLAG, ETIMSK,1<<2},
  {OCIE3B_FLAG,ETIMSK,1<<3},
  {OCIE3A_FLAG,ETIMSK,1<<4},
  {TICIE3_FLAG,ETIMSK,1<<5},

  {OCF1C_FLAG, ETIFR, 1<<0},
  {OCF3C_FLAG, ETIFR, 1<<1},
  {TOV3_FLAG,  ETIFR, 1<<2},
  {OCF3B_FLAG, ETIFR, 1<<3},
  {OCF3A_FLAG, ETIFR, 1<<4},
  {ICF3_FLAG,  ETIFR, 1<<5},

  {FOC1C_FLAG, TCCR1C,1<<5},
  {FOC1B_FLAG, TCCR1C,1<<6},
  {FOC1A_FLAG, TCCR1C,1<<7},

  {TWIE_FLAG,  TWCR,  1<<0},
  {TWEN_FLAG,  TWCR,  1<<2},
  {TWWC_FLAG,  TWCR,  1<<3},
  {TWSTO_FLAG, TWCR,  1<<4},
  {TWSTA_FLAG, TWCR,  1<<5},
  {TWEA_FLAG,  TWCR,  1<<6},
  {TWINT_FLAG, TWCR,  1<<7},

  {TWGCE_FLAG, TWAR,  1<<0},

  {SRW11_FLAG, XMCRA, 1<<1},
  {SRW00_FLAG, XMCRA, 1<<2},
  {SRW01_FLAG, XMCRA, 1<<3},
  {SRL0_FLAG,  XMCRA, 1<<4},
  {SRL1_FLAG,  XMCRA, 1<<5},
  {SRL2_FLAG,  XMCRA, 1<<6},

  {XMM0_FLAG,  XMCRB, 1<<0},
  {XMM1_FLAG,  XMCRB, 1<<1},
  {XMM2_FLAG,  XMCRB, 1<<2},
  {XMBK_FLAG,  XMCRB, 1<<3},

  {ISC00_FLAG, EICRA, 1<<0},
  {ISC01_FLAG, EICRA, 1<<1},
  {ISC10_FLAG, EICRA, 1<<2},
  {ISC11_FLAG, EICRA, 1<<3},
  {ISC20_FLAG, EICRA, 1<<4},
  {ISC21_FLAG, EICRA, 1<<5},
  {ISC30_FLAG, EICRA, 1<<6},
  {ISC31_FLAG, EICRA, 1<<7},

  {SPMEN_FLAG, SPMCR, 1<<0},
  {PGERS_FLAG, SPMCR, 1<<1},
  {PGWRT_FLAG, SPMCR, 1<<2},
  {BLBSET_FLAG,SPMCR, 1<<3},
  {RWWSRE_FLAG,SPMCR, 1<<4},
  {RWWSB_FLAG, SPMCR, 1<<6},
  {SPMIE_FLAG, SPMCR, 1<<7},

  {ISC40_FLAG, EICRB, 1<<0},
  {ISC41_FLAG, EICRB, 1<<1},
  {ISC50_FLAG, EICRB, 1<<2},
  {ISC51_FLAG, EICRB, 1<<3},
  {ISC60_FLAG, EICRB, 1<<4},
  {ISC61_FLAG, EICRB, 1<<5},
  {ISC70_FLAG, EICRB, 1<<6},
  {ISC71_FLAG, EICRB, 1<<7},

  {INT0_FLAG,  EIMSK, 1<<0},
  {INT1_FLAG,  EIMSK, 1<<1},
  {INT2_FLAG,  EIMSK, 1<<2},
  {INT3_FLAG,  EIMSK, 1<<3},
  {INT4_FLAG,  EIMSK, 1<<4},
  {INT5_FLAG,  EIMSK, 1<<5},
  {INT6_FLAG,  EIMSK, 1<<6},
  {INT7_FLAG,  EIMSK, 1<<7},
  
  {INTF0_FLAG, EIFR,  1<<0},
  {INTF1_FLAG, EIFR,  1<<1},
  {INTF2_FLAG, EIFR,  1<<2},
  {INTF3_FLAG, EIFR,  1<<3},
  {INTF4_FLAG, EIFR,  1<<4},
  {INTF5_FLAG, EIFR,  1<<5},
  {INTF6_FLAG, EIFR,  1<<6},
  {INTF7_FLAG, EIFR,  1<<7},

  {TOIE0_FLAG, TIMSK, 1<<0},
  {OCIE0_FLAG, TIMSK, 1<<1},
  {TOIE1_FLAG, TIMSK, 1<<2},
  {OCIE1B_FLAG,TIMSK, 1<<3},
  {OCIE1A_FLAG,TIMSK, 1<<4},
  {TICIE1_FLAG,TIMSK, 1<<5},
  {TOIE2_FLAG, TIMSK, 1<<6},
  {OCIE2_FLAG, TIMSK, 1<<7},
  
  {TOV0_FLAG,  TIFR,  1<<0},
  {OCF0_FLAG,  TIFR,  1<<1},
  {TOV1_FLAG,  TIFR,  1<<2},
  {OCF1B_FLAG, TIFR,  1<<3},
  {OCF1A_FLAG, TIFR,  1<<4},
  {ICF1_FLAG,  TIFR,  1<<5},
  {TOV2_FLAG,  TIFR,  1<<6},
  {OCF2_FLAG,  TIFR,  1<<7},

  {IVCE_FLAG,  MCUCR, 1<<0},
  {IVSEL_FLAG, MCUCR, 1<<1},
  {SM2_FLAG,   MCUCR, 1<<2},
  {SM0_FLAG,   MCUCR, 1<<3},
  {SM1_FLAG,   MCUCR, 1<<4},
  {SE_FLAG,    MCUCR, 1<<5},
  {SRW10_FLAG, MCUCR, 1<<6},
  {SRE_FLAG,   MCUCR, 1<<7},
 
  {PORF_FLAG,  MCUSR, 1<<0},   
  {EXTRF_FLAG, MCUSR, 1<<1},    
  {BORF_FLAG,  MCUSR, 1<<2},
  {WDRF_FLAG,  MCUSR, 1<<3},
  {JTRF_FLAG,  MCUSR, 1<<4},
  {JTD_FLAG,   MCUSR, 1<<7},

  {CS00_FLAG,  TCCR0, 1<<0},
  {CS01_FLAG,  TCCR0, 1<<1},
  {CS02_FLAG,  TCCR0, 1<<2},
  {WGM01_FLAG, TCCR0, 1<<3},
  {COM00_FLAG, TCCR0, 1<<4},
  {COM01_FLAG, TCCR0, 1<<5},
  {WGM00_FLAG, TCCR0, 1<<6},
  {FOC0_FLAG,  TCCR0, 1<<7},

  {TCR0UB_FLAG,ASSR,  1<<0},
  {OCR0UB_FLAG,ASSR,  1<<1},
  {TCN0UB_FLAG,ASSR,  1<<2},
  {AS0_FLAG,   ASSR,  1<<3},

  {WGM10_FLAG, TCCR1A,1<<0},
  {WGM11_FLAG, TCCR1A,1<<1},
  {COM1C0_FLAG,TCCR1A,1<<2},
  {COM1C1_FLAG,TCCR1A,1<<3},
  {COM1B0_FLAG,TCCR1A,1<<4},
  {COM1B1_FLAG,TCCR1A,1<<5},
  {COM1A0_FLAG,TCCR1A,1<<6},
  {COM1A1_FLAG,TCCR1A,1<<7},

  {CS10_FLAG,  TCCR1B,1<<0},
  {CS11_FLAG,  TCCR1B,1<<1},
  {CS12_FLAG,  TCCR1B,1<<2},
  {WGM12_FLAG, TCCR1B,1<<3},
  {WGM13_FLAG, TCCR1B,1<<4},
  {ICES1_FLAG, TCCR1B,1<<6},
  {ICNC1_FLAG, TCCR1B,1<<7},

  {CS20_FLAG,  TCCR2, 1<<0},
  {CS21_FLAG,  TCCR2, 1<<1},
  {CS22_FLAG,  TCCR2, 1<<2},
  {WGM21_FLAG, TCCR2, 1<<3},
  {COM20_FLAG, TCCR2, 1<<4},
  {COM21_FLAG, TCCR2, 1<<5},
  {WGM20_FLAG, TCCR2, 1<<6},
  {FOC2_FLAG,  TCCR2, 1<<7},

  {WDP0_FLAG,  WDTCR, 1<<0},
  {WDP1_FLAG,  WDTCR, 1<<1},
  {WDP2_FLAG,  WDTCR, 1<<2},
  {WDE_FLAG,   WDTCR, 1<<3},
  {WDTOE_FLAG, WDTCR, 1<<4},

  {PSR321_FLAG,SFIOR, 1<<0},
  {PSR0_FLAG,  SFIOR, 1<<1},
  {PUD_FLAG,   SFIOR, 1<<2},
  {ACME_FLAG,  SFIOR, 1<<3},
  {ADHSM_FLAG, SFIOR, 1<<4},
  {TSM_FLAG,   SFIOR, 1<<7},

  {EERE_FLAG,  EECR,  1<<0},
  {EEWE_FLAG,  EECR,  1<<1},
  {EEMWE_FLAG, EECR,  1<<2},
  {EERIE_FLAG, EECR,  1<<3},

  {SPI2X_FLAG, SPSR,  1<<0},
  {WCOL_FLAG,  SPSR,  1<<6},
  {SPIF_FLAG,  SPSR,  1<<7},

  {SPR0_FLAG,  SPCR,  1<<0},
  {SPR1_FLAG,  SPCR,  1<<1},
  {CPHA_FLAG,  SPCR,  1<<2},
  {CPOL_FLAG,  SPCR,  1<<3},
  {MSTR_FLAG,  SPCR,  1<<4},
  {DORD_FLAG,  SPCR,  1<<5},
  {SPE_FLAG,   SPCR,  1<<6},
  {SPIE_FLAG,  SPCR,  1<<7},

  {MPCM0_FLAG, UCSR0A,1<<0},
  {U2X0_FLAG,  UCSR0A,1<<1},
  {PE0_FLAG,   UCSR0A,1<<2},
  {DOR0_FLAG,  UCSR0A,1<<3},
  {FE0_FALG,   UCSR0A,1<<4},
  {UDRE0_FLAG, UCSR0A,1<<5},
  {TXC0_FLAG,  UCSR0A,1<<6},
  {RXC0_FLAG,  UCSR0A,1<<7},

  {TXB80_FLAG, UCSR0B,1<<0},
  {RXB80_FLAG, UCSR0B,1<<1},
  {UCSZ02_FLAG,UCSR0B,1<<2},
  {TXEN0_FLAG, UCSR0B,1<<3},
  {RXEN0_FLAG, UCSR0B,1<<4},
  {UDRIE0_FLAG,UCSR0B,1<<5},
  {TXCIE0_FLAG,UCSR0B,1<<6},
  {RXCIE0_FLAG,UCSR0B,1<<7},

  {ACIS0_FLAG, ACSR,  1<<0},
  {ACIS1_FLAG, ACSR,  1<<1},
  {ACIC_FLAG,  ACSR,  1<<2},
  {ACIE_FLAG,  ACSR,  1<<3},
  {ACI_FLAG,   ACSR,  1<<4},
  {ACO_FLAG,   ACSR,  1<<5},
  {ACBG_FLAG,  ACSR,  1<<6},
  {ACD_FLAG,   ACSR,  1<<7},

  {MUX0_FLAG,  ADMUX, 1<<0},
  {MUX1_FLAG,  ADMUX, 1<<1},
  {MUX2_FLAG,  ADMUX, 1<<2},
  {MUX3_FLAG,  ADMUX, 1<<3},
  {MUX4_FLAG,  ADMUX, 1<<4},
  {ADLAR_FLAG, ADMUX, 1<<5},
  {REFS0_FLAG, ADMUX, 1<<6},
  {REFS1_FLAG, ADMUX, 1<<7},

  {ADPS0_FLAG, ADCSR, 1<<0},
  {ADPS1_FLAG, ADCSR, 1<<1},
  {ADPS2_FLAG, ADCSR, 1<<2},
  {ADIE_FLAG,  ADCSR, 1<<3},
  {ADIF_FLAG,  ADCSR, 1<<4},
  {ADFR_FLAG,  ADCSR, 1<<5},
  {ADSC_FLAG,  ADCSR, 1<<6},
  {ADEN_FLAG,  ADCSR, 1<<7},
  
  {-1,-1}
};