atmega161.h

linux上实现的多种型号的AVR模拟器

int atmega161_int[]={
  RESET,INT0,INT1,INT2,TIMER2_COMP,TIMER2_OVF,TIMER1_CAPT,TIMER1_COMPA,
  TIMER1_COMPB,TIMER1_OVF,TIMER0_COMP,TIMER0_OVF,SPI_STC,UART0_RX,UART1_RX,
  UART0_UDRE,UART1_UDRE,UART0_TX,UART1_TX,EE_READY,ANALOG_COMP,-1};


IO_port atmega161_io[]={
  {SREG,  0x3F,0xFF,0xFF,0},
  {SPH,   0x3E,0xFF,0xFF,0},
  {SPL,   0x3D,0xFF,0xFF,0},
  {GIMSK, 0x3B,0xE0,0xE0,0},
  {GIFR,  0x3A,0xE0,0xE0,0},
  {TIMSK, 0x39,0xFF,0xFF,0},
  {TIFR,  0x38,0xFF,0xFF,0},
  {SPMCR, 0x37,0x0F,0x0F,0},
  {EMCUCR,0x36,0xFF,0xFF,0},
  {MCUCR, 0x35,0xFF,0xFF,0},
  {MCUSR, 0x34,0x0F,0x0F,0},
  {TCCR0, 0x33,0xFF,0xFF,0},
  {TCNT0, 0x32,0xFF,0xFF,0},
  {OCR0,  0x31,0xFF,0xFF,0},
  {SFIOR, 0x30,0x03,0x03,0},
  {TCCR1A,0x2F,0xFF,0xFF,0},
  {TCCR1B,0x2E,0xCF,0xCF,0},
  {TCNT1H,0x2D,0xFF,0xFF,0},
  {TCNT1L,0x2C,0xFF,0xFF,0},
  {OCR1AH,0x2B,0xFF,0xFF,0},
  {OCR1AL,0x2A,0xFF,0xFF,0},
  {OCR1BH,0x29,0xFF,0xFF,0},
  {OCR1BL,0x28,0xFF,0xFF,0},
  {TCCR2, 0x27,0xFF,0xFF,0},
  {ASSR,  0x26,0x08,0x0F,0},
  {ICR1H, 0x25,0x00,0xFF,0},
  {ICR1L, 0x24,0x00,0xFF,0},
  {TCNT2, 0x23,0xFF,0xFF,0},
  {OCR2,  0x22,0xFF,0xFF,0},
  {WDTCR, 0x21,0x1F,0x1F,0},
  {UBRRHI,0x20,0xFF,0xFF,0},
  {EEARH, 0x1F,0x01,0x01,0},
  {EEARL, 0x1E,0xFF,0xFF,0},
  {EEDR,  0x1D,0xFF,0xFF,0},
  {EECR,  0x1C,0x0F,0x0F,0},
  {PORTA, 0x1B,0xFF,0xFF,0},
  {DDRA,  0x1A,0xFF,0xFF,0},
  {PINA,  0x19,0x00,0xFF,0},
  {PORTB, 0x18,0xFF,0xFF,0},
  {DDRB,  0x17,0xFF,0xFF,0},
  {PINB,  0x16,0x00,0xFF,0},
  {PORTC, 0x15,0xFF,0xFF,0},
  {DDRC,  0x14,0xFF,0xFF,0},
  {PINC,  0x13,0x00,0xFF,0},
  {PORTD, 0x12,0xFF,0xFF,0},
  {DDRD,  0x11,0xFF,0xFF,0},
  {PIND,  0x10,0x00,0xFF,0},
  {SPDR,  0x0F,0xFF,0xFF,0},
  {SPSR,  0x0E,0x01,0xC1,0},
  {SPCR,  0x0D,0xFF,0xFF,0},
  {UDR0,  0x0C,0xFF,0xFF,0},
  {UCSR0A,0x0B,0x43,0xFB,0x20},
  {UCSR0B,0x0A,0xFD,0xFF,0x02},
  {UBRR0L,0x09,0xFF,0xFF,0},
  {ACSR,  0x08,0x9F,0xFF,0},
  {PORTE, 0x07,0x07,0x07,0},
  {DDRE,  0x06,0x07,0x07,0},
  {PINE,  0x05,0x00,0x07,0},
  {UDR1,  0x03,0xFF,0xFF,0},
  {UCSR1A,0x02,0x40,0xFB,0x20},
  {UCSR1B,0x01,0xFD,0xFF,0x02},
  {UBRR1L,0x00,0xFF,0xFF,0},
  {-1,0,0,0}
};

Pin atmega161_pins[]={
  {OC0_PIN, 0x18,0x16,1<<0},{T0_PIN,  0x18,0x16,1<<0},
  {OC2_PIN, 0x18,0x16,1<<1},{T1_PIN,  0x18,0x16,1<<1},
  {RXD1_PIN,0x18,0x16,1<<2},{AIN0_PIN,0x18,0x16,1<<2},
  {TXD1_PIN,0x18,0x16,1<<3},{AIN1_PIN,0x18,0x16,1<<3},
  {SS_PIN,  0x18,0x16,1<<4},
  {MOSI_PIN,0x18,0x16,1<<5},
  {MISO_PIN,0x18,0x16,1<<6},
  {SCK_PIN, 0x18,0x16,1<<7},
  
  {RXD0_PIN,0x12,0x10,1<<0},
  {TXD0_PIN,0x12,0x10,1<<1},
  {INT0_PIN,0x12,0x10,1<<2},
  {INT1_PIN,0x12,0x10,1<<3},
  {TOSC1_PIN,0x12,0x10,1<<4},
  {TOSC2_PIN,0x12,0x10,1<<5},{OC1A_PIN,0x12,0x10,1<<5},
  {WR_PIN,  0x12,0x10,1<<6},
  {RD_PIN,  0x12,0x10,1<<7},

  {IC1_PIN, 0x07,0x05,1<<0},{INT2_PIN,0x07,0x05,1<<0},
  {ALE_PIN, 0x07,0x05,1<<1},
  {OC1B_PIN,0x07,0x05,1<<2},
  
  {-1,0,0,0}
};

Flag atmega161_flags[]={
  {INT2_FLAG,  GICR,  1<<5},
  {INT0_FLAG,  GICR,  1<<6},
  {INT1_FLAG,  GICR,  1<<7},

  {INTF2_FLAG, GIFR,  1<<5},
  {INTF0_FLAG, GIFR,  1<<6},
  {INTF1_FLAG, GIFR,  1<<7},

  {OCIE0_FLAG, TIMSK, 1<<0},
  {TOIE0_FLAG, TIMSK, 1<<1},
  {OCIE2_FLAG, TIMSK, 1<<2},
  {TICIE1_FLAG,TIMSK, 1<<3},
  {TOIE2_FLAG, TIMSK, 1<<4},
  {OCIE1B_FLAG,TIMSK, 1<<5},
  {OCIE1A_FLAG,TIMSK, 1<<6},
  {TOIE1_FLAG, TIMSK, 1<<7},
  
  {OCF0_FLAG,  TIFR,  1<<0},
  {TOV0_FLAG,  TIFR,  1<<1},
  {OCF2_FLAG,  TIFR,  1<<2},
  {ICF1_FLAG,  TIFR,  1<<3},
  {TOV2_FLAG,  TIFR,  1<<4},
  {OCF1B_FLAG, TIFR,  1<<5},
  {OCF1A_FLAG, TIFR,  1<<6},
  {TOV1_FLAG,  TIFR,  1<<7},

  {SPMEN_FLAG, SPMCR, 1<<0},
  {PGERS_FLAG, SPMCR, 1<<1},
  {PGWRT_FLAG, SPMCR, 1<<2},
  {LBSET_FLAG, SPMCR, 1<<3},

  {ISC2_FLAG,  EMCUCR,1<<0},
  {SRW11_FLAG, EMCUCR,1<<1},
  {SRW00_FLAG, EMCUCR,1<<2},
  {SRW01_FLAG, EMCUCR,1<<3},
  {SRL0_FLAG,  EMCUCR,1<<4},
  {SRL1_FLAG,  EMCUCR,1<<5},
  {SRL2_FLAG,  EMCUCR,1<<6},
  {SM0_FLAG,   EMCUCR,1<<7},

  {ISC00_FLAG, MCUCR, 1<<0},
  {ISC01_FLAG, MCUCR, 1<<1},
  {ISC10_FLAG, MCUCR, 1<<2},
  {ISC11_FLAG, MCUCR, 1<<3},
  {SM1_FLAG,   MCUCR, 1<<4},
  {SE_FLAG,    MCUCR, 1<<5},
  {SRW10_FLAG, MCUCR, 1<<6},
  {SRE_FLAG,   MCUCR, 1<<7},
 
  {PORF_FLAG,  MCUSR, 1<<0},   
  {EXTRF_FLAG, MCUSR, 1<<1},    
  {BORF_FLAG,  MCUSR, 1<<2},
  {WDRF_FLAG,  MCUSR, 1<<3},

  {CS00_FLAG,  TCCR0, 1<<0},
  {CS01_FLAG,  TCCR0, 1<<1},
  {CS02_FLAG,  TCCR0, 1<<2},
  {CTC0_FLAG,  TCCR0, 1<<3},
  {COM00_FLAG, TCCR0, 1<<4},
  {COM01_FLAG, TCCR0, 1<<5},
  {PWM0_FLAG,  TCCR0, 1<<6},
  {FOC0_FLAG,  TCCR0, 1<<7},

  {PSR10_FLAG, SFIOR, 1<<0},
  {PSR2_FLAG,  SFIOR, 1<<1},

  {PWM10_FLAG, TCCR1A,1<<0},
  {PWM11_FLAG, TCCR1A,1<<1},
  {FOC1B_FLAG, TCCR1A,1<<2},
  {FOC1A_FLAG, TCCR1A,1<<3},
  {COM1B0_FLAG,TCCR1A,1<<4},
  {COM1B1_FLAG,TCCR1A,1<<5},
  {COM1A0_FLAG,TCCR1A,1<<6},
  {COM1A1_FLAG,TCCR1A,1<<7},

  {CS10_FLAG,  TCCR1B,1<<0},
  {CS11_FLAG,  TCCR1B,1<<1},
  {CS12_FLAG,  TCCR1B,1<<2},
  {CTC1_FLAG,  TCCR1B,1<<3},
  {ICES1_FLAG, TCCR1B,1<<6},
  {ICNC1_FLAG, TCCR1B,1<<7},

  {CS20_FLAG,  TCCR2, 1<<0},
  {CS21_FLAG,  TCCR2, 1<<1},
  {CS22_FLAG,  TCCR2, 1<<2},
  {CTC2_FLAG,  TCCR2, 1<<3},
  {COM20_FLAG, TCCR2, 1<<4},
  {COM21_FLAG, TCCR2, 1<<5},
  {PWM2_FLAG,  TCCR2, 1<<6},
  {FOC2_FLAG,  TCCR2, 1<<7},

  {TCR2UB_FLAG,ASSR,  1<<0},
  {OCR2UB_FLAG,ASSR,  1<<1},
  {TCN2UB_FLAG,ASSR,  1<<2},
  {AS2_FLAG,   ASSR,  1<<3},

  {WDP0_FLAG,  WDTCR, 1<<0},
  {WDP1_FLAG,  WDTCR, 1<<1},
  {WDP2_FLAG,  WDTCR, 1<<2},
  {WDE_FLAG,   WDTCR, 1<<3},
  {WDTOE_FLAG, WDTCR, 1<<4},

  {EERE_FLAG,  EECR,  1<<0},
  {EEWE_FLAG,  EECR,  1<<1},
  {EEMWE_FLAG, EECR,  1<<2},
  {EERIE_FLAG, EECR,  1<<3},

  {SPI2X_FLAG, SPSR,  1<<0},
  {WCOL_FLAG,  SPSR,  1<<6},
  {SPIF_FLAG,  SPSR,  1<<7},

  {SPR0_FLAG,  SPCR,  1<<0},
  {SPR1_FLAG,  SPCR,  1<<1},
  {CPHA_FLAG,  SPCR,  1<<2},
  {CPOL_FLAG,  SPCR,  1<<3},
  {MSTR_FLAG,  SPCR,  1<<4},
  {DORD_FLAG,  SPCR,  1<<5},
  {SPE_FLAG,   SPCR,  1<<6},
  {SPIE_FLAG,  SPCR,  1<<7},

  {MPCM0_FLAG, UCSR0A,1<<0},
  {U2X0_FLAG,  UCSR0A,1<<1},
  {OR0_FLAG,   UCSR0A,1<<3},
  {FE0_FALG,   UCSR0A,1<<4},
  {UDRE0_FLAG, UCSR0A,1<<5},
  {TXC0_FLAG,  UCSR0A,1<<6},
  {RXC0_FLAG,  UCSR0A,1<<7},

  {TXB80_FLAG, UCSR0B,1<<0},
  {RXB80_FLAG, UCSR0B,1<<1},
  {CHR90_FLAG, UCSR0B,1<<2},
  {TXEN0_FLAG, UCSR0B,1<<3},
  {RXEN0_FLAG, UCSR0B,1<<4},
  {UDRIE0_FLAG,UCSR0B,1<<5},
  {TXCIE0_FLAG,UCSR0B,1<<6},
  {RXCIE0_FLAG,UCSR0B,1<<7},

  {ACIS0_FLAG, ACSR,  1<<0},
  {ACIS1_FLAG, ACSR,  1<<1},
  {ACIC_FLAG,  ACSR,  1<<2},
  {ACIE_FLAG,  ACSR,  1<<3},
  {ACI_FLAG,   ACSR,  1<<4},
  {ACO_FLAG,   ACSR,  1<<5},
  {AINBG_FLAG, ACSR,  1<<6},
  {ACD_FLAG,   ACSR,  1<<7},

  {MPCM1_FLAG, UCSR1A,1<<0},
  {U2X1_FLAG,  UCSR1A,1<<1},
  {OR1_FLAG,   UCSR1A,1<<3},
  {FE1_FALG,   UCSR1A,1<<4},
  {UDRE1_FLAG, UCSR1A,1<<5},
  {TXC1_FLAG,  UCSR1A,1<<6},
  {RXC1_FLAG,  UCSR1A,1<<7},

  {TXB81_FLAG, UCSR1B,1<<0},
  {RXB81_FLAG, UCSR1B,1<<1},
  {CHR91_FLAG, UCSR1B,1<<2},
  {TXEN1_FLAG, UCSR1B,1<<3},
  {RXEN1_FLAG, UCSR1B,1<<4},
  {UDRIE1_FLAG,UCSR1B,1<<5},
  {TXCIE1_FLAG,UCSR1B,1<<6},
  {RXCIE1_FLAG,UCSR1B,1<<7},
  {-1,-1}
};