freqtest.map.qmsg

学verilog时写的8位十进制频率计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Oct 04 10:24:43 2008 " "Info: Processing started: Sat Oct 04 10:24:43 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off freqtest -c freqtest " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off freqtest -c freqtest" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../scan_led/scan_led.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../scan_led/scan_led.v" { { "Info" "ISGN_ENTITY_NAME" "1 scan_led " "Info: Found entity 1: scan_led" {  } { { "../scan_led/scan_led.v" "" { Text "F:/verilog 学习/scan_led/scan_led.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "freqtest.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file freqtest.v" { { "Info" "ISGN_ENTITY_NAME" "1 freqtest " "Info: Found entity 1: freqtest" {  } { { "freqtest.v" "" { Text "F:/verilog 学习/8位十进制频率计/freqtest.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cnt10.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file cnt10.v" { { "Info" "ISGN_ENTITY_NAME" "1 cnt10 " "Info: Found entity 1: cnt10" {  } { { "cnt10.v" "" { Text "F:/verilog 学习/8位十进制频率计/cnt10.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "freqtest " "Info: Elaborating entity \"freqtest\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Error" "EVRFX_VERI_NOT_A_STRUCTURAL_NET_EXPRESSION" "dout freqtest.v(41) " "Error (10663): Verilog HDL Port Connection error at freqtest.v(41): output or inout port \"dout\" must be connected to a structural net expression" {  } { { "freqtest.v" "" { Text "F:/verilog 学习/8位十进制频率计/freqtest.v" 41 0 0 } }  } 0 10663 "Verilog HDL Port Connection error at %2!s!: output or inout port \"%1!s!\" must be connected to a structural net expression" 0 0}
{ "Error" "ESGN_TOP_HIER_ELABORATION_FAILURE" "" "Error: Can't elaborate top-level user hierarchy" {  } {  } 0 0 "Can't elaborate top-level user hierarchy" 0 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 0 warnings" { { "Error" "EQEXE_END_BANNER_TIME" "Sat Oct 04 10:24:43 2008 " "Error: Processing ended: Sat Oct 04 10:24:43 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:01 " "Error: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}