cnt10.v

学verilog时写的8位十进制频率计

module cnt10(clock,rst,cin,cout,dout);
	input clock;
	input cin;
	input rst;
	output cout;
	output[3:0] dout;
	reg[3:0] counter;
	
	assign dout=counter;
	assign cout=cin&&(counter>=4'd9);
	always@(posedge clock or posedge rst)
		begin
			if(rst)
				counter<=4'd0;
			else if(cin)
				begin
					if(cout)
						counter<=4'd0;
					else 
						counter<=counter+1'b1;
				end
				
		end
		
endmodule