2.txt

设计一个简单的8比特ALU和一个简单的存储器

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    15:13:49 05/24/08
// Design Name:    
// Module Name:    laji
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module YUNSUAN32(AD,D,WR,RD,DOUT);
 parameter D_WIDTH = 5;
   parameter A_WIDTH = 8;

	input[D_WIDTH-1:0] AD;
	input[A_WIDTH-1:0] D;
	input WR,RD;
	output[A_WIDTH-1:0]DOUT;
	 
   reg  [D_WIDTH-1:0] ram [(2**A_WIDTH)-1:0];
   wire [A_WIDTH-1:0] DOUT;
	
  ram164 ram_324(.din(AD[3:0]),.addr(D[3:0]),.wr(WR),.rd(RD),.cs(AD[4]),.dout(DOUT[3:0]));
  ram164 ram_328(.din(AD[3:0]),.addr(D[7:4]),.wr(WR),.rd(RD),.cs(AD[4]),.dout(DOUT[7:4]));
  ram164 ram_3212(.din(AD[3:0]),.addr(D[3:0]),.wr(WR),.rd(RD),.cs(~AD[4]),.dout(DOUT[3:0]));
  ram164 ram_3216(.din(AD[3:0]),.addr(D[7:4]),.wr(WR),.rd(RD),.cs(~AD[4]),.dout(DOUT[7:4]));





endmodule

module ram164(din,addr,wr,rd,cs,dout);
  
   parameter D_WIDTH = 4;
   parameter A_WIDTH = 4;

	input[D_WIDTH-1:0] din;
	input[A_WIDTH-1:0] addr;
	input wr,rd,cs;
	output[D_WIDTH-1:0]dout;
	 
   reg  [D_WIDTH-1:0] ram [(2**A_WIDTH)-1:0];
   wire [D_WIDTH-1:0] dout;
  
   
   always @(posedge wr)
      if (!cs)
         ram[addr] <= din;

   assign dout = (!(rd||cs))?ram[addr]:4'bzzzz; 
endmodule