mcf548x_sec.h

freescale MCF5485EVB开发板上中断操作示例

#define MCF_SEC_CCPSRLn_SRD             (0x00040000)
#define MCF_SEC_CCPSRLn_PRD             (0x00080000)
#define MCF_SEC_CCPSRLn_SG              (0x00100000)
#define MCF_SEC_CCPSRLn_PG              (0x00200000)
#define MCF_SEC_CCPSRLn_SR              (0x00400000)
#define MCF_SEC_CCPSRLn_PR              (0x00800000)
#define MCF_SEC_CCPSRLn_MO              (0x01000000)
#define MCF_SEC_CCPSRLn_MI              (0x02000000)
#define MCF_SEC_CCPSRLn_STAT            (0x04000000)

/* Bit definitions and macros for MCF_SEC_AFRCR */
#define MCF_SEC_AFRCR_SR                (0x01000000)
#define MCF_SEC_AFRCR_MI                (0x02000000)
#define MCF_SEC_AFRCR_RI                (0x04000000)

/* Bit definitions and macros for MCF_SEC_AFSR */
#define MCF_SEC_AFSR_RD                 (0x01000000)
#define MCF_SEC_AFSR_ID                 (0x02000000)
#define MCF_SEC_AFSR_IE                 (0x04000000)
#define MCF_SEC_AFSR_OFE                (0x08000000)
#define MCF_SEC_AFSR_IFW                (0x10000000)
#define MCF_SEC_AFSR_HALT               (0x20000000)

/* Bit definitions and macros for MCF_SEC_AFISR */
#define MCF_SEC_AFISR_DSE               (0x00010000)
#define MCF_SEC_AFISR_KSE               (0x00020000)
#define MCF_SEC_AFISR_CE                (0x00040000)
#define MCF_SEC_AFISR_ERE               (0x00080000)
#define MCF_SEC_AFISR_IE                (0x00100000)
#define MCF_SEC_AFISR_OFU               (0x02000000)
#define MCF_SEC_AFISR_IFO               (0x04000000)
#define MCF_SEC_AFISR_IFE               (0x10000000)
#define MCF_SEC_AFISR_OFE               (0x20000000)
#define MCF_SEC_AFISR_AE                (0x40000000)
#define MCF_SEC_AFISR_ME                (0x80000000)

/* Bit definitions and macros for MCF_SEC_AFIMR */
#define MCF_SEC_AFIMR_DSE               (0x00010000)
#define MCF_SEC_AFIMR_KSE               (0x00020000)
#define MCF_SEC_AFIMR_CE                (0x00040000)
#define MCF_SEC_AFIMR_ERE               (0x00080000)
#define MCF_SEC_AFIMR_IE                (0x00100000)
#define MCF_SEC_AFIMR_OFU               (0x02000000)
#define MCF_SEC_AFIMR_IFO               (0x04000000)
#define MCF_SEC_AFIMR_IFE               (0x10000000)
#define MCF_SEC_AFIMR_OFE               (0x20000000)
#define MCF_SEC_AFIMR_AE                (0x40000000)
#define MCF_SEC_AFIMR_ME                (0x80000000)

/* Bit definitions and macros for MCF_SEC_DRCR */
#define MCF_SEC_DRCR_SR                 (0x01000000)
#define MCF_SEC_DRCR_MI                 (0x02000000)
#define MCF_SEC_DRCR_RI                 (0x04000000)

/* Bit definitions and macros for MCF_SEC_DSR */
#define MCF_SEC_DSR_RD                  (0x01000000)
#define MCF_SEC_DSR_ID                  (0x02000000)
#define MCF_SEC_DSR_IE                  (0x04000000)
#define MCF_SEC_DSR_OFR                 (0x08000000)
#define MCF_SEC_DSR_IFW                 (0x10000000)
#define MCF_SEC_DSR_HALT                (0x20000000)

/* Bit definitions and macros for MCF_SEC_DISR */
#define MCF_SEC_DISR_DSE                (0x00010000)
#define MCF_SEC_DISR_KSE                (0x00020000)
#define MCF_SEC_DISR_CE                 (0x00040000)
#define MCF_SEC_DISR_ERE                (0x00080000)
#define MCF_SEC_DISR_IE                 (0x00100000)
#define MCF_SEC_DISR_KPE                (0x00200000)
#define MCF_SEC_DISR_OFU                (0x02000000)
#define MCF_SEC_DISR_IFO                (0x04000000)
#define MCF_SEC_DISR_IFE                (0x10000000)
#define MCF_SEC_DISR_OFE                (0x20000000)
#define MCF_SEC_DISR_AE                 (0x40000000)
#define MCF_SEC_DISR_ME                 (0x80000000)

/* Bit definitions and macros for MCF_SEC_DIMR */
#define MCF_SEC_DIMR_DSE                (0x00010000)
#define MCF_SEC_DIMR_KSE                (0x00020000)
#define MCF_SEC_DIMR_CE                 (0x00040000)
#define MCF_SEC_DIMR_ERE                (0x00080000)
#define MCF_SEC_DIMR_IE                 (0x00100000)
#define MCF_SEC_DIMR_KPE                (0x00200000)
#define MCF_SEC_DIMR_OFU                (0x02000000)
#define MCF_SEC_DIMR_IFO                (0x04000000)
#define MCF_SEC_DIMR_IFE                (0x10000000)
#define MCF_SEC_DIMR_OFE                (0x20000000)
#define MCF_SEC_DIMR_AE                 (0x40000000)
#define MCF_SEC_DIMR_ME                 (0x80000000)

/* Bit definitions and macros for MCF_SEC_MDRCR */
#define MCF_SEC_MDRCR_SR                (0x01000000)
#define MCF_SEC_MDRCR_MI                (0x02000000)
#define MCF_SEC_MDRCR_RI                (0x04000000)

/* Bit definitions and macros for MCF_SEC_MDSR */
#define MCF_SEC_MDSR_RD                 (0x01000000)
#define MCF_SEC_MDSR_ID                 (0x02000000)
#define MCF_SEC_MDSR_IE                 (0x04000000)
#define MCF_SEC_MDSR_IFW                (0x10000000)
#define MCF_SEC_MDSR_HALT               (0x20000000)

/* Bit definitions and macros for MCF_SEC_MDISR */
#define MCF_SEC_MDISR_DSE               (0x00010000)
#define MCF_SEC_MDISR_KSE               (0x00020000)
#define MCF_SEC_MDISR_CE                (0x00040000)
#define MCF_SEC_MDISR_ERE               (0x00080000)
#define MCF_SEC_MDISR_IE                (0x00100000)
#define MCF_SEC_MDISR_IFO               (0x04000000)
#define MCF_SEC_MDISR_AE                (0x40000000)
#define MCF_SEC_MDISR_ME                (0x80000000)

/* Bit definitions and macros for MCF_SEC_MDIMR */
#define MCF_SEC_MDIMR_DSE               (0x00010000)
#define MCF_SEC_MDIMR_KSE               (0x00020000)
#define MCF_SEC_MDIMR_CE                (0x00040000)
#define MCF_SEC_MDIMR_ERE               (0x00080000)
#define MCF_SEC_MDIMR_IE                (0x00100000)
#define MCF_SEC_MDIMR_IFO               (0x04000000)
#define MCF_SEC_MDIMR_AE                (0x40000000)
#define MCF_SEC_MDIMR_ME                (0x80000000)

/* Bit definitions and macros for MCF_SEC_RNGRCR */
#define MCF_SEC_RNGRCR_SR               (0x01000000)
#define MCF_SEC_RNGRCR_MI               (0x02000000)
#define MCF_SEC_RNGRCR_RI               (0x04000000)

/* Bit definitions and macros for MCF_SEC_RNGSR */
#define MCF_SEC_RNGSR_RD                (0x01000000)
#define MCF_SEC_RNGSR_O                 (0x02000000)
#define MCF_SEC_RNGSR_IE                (0x04000000)
#define MCF_SEC_RNGSR_OFR               (0x08000000)
#define MCF_SEC_RNGSR_HALT              (0x20000000)

/* Bit definitions and macros for MCF_SEC_RNGISR */
#define MCF_SEC_RNGISR_IE               (0x00100000)
#define MCF_SEC_RNGISR_OFU              (0x02000000)
#define MCF_SEC_RNGISR_AE               (0x40000000)
#define MCF_SEC_RNGISR_ME               (0x80000000)

/* Bit definitions and macros for MCF_SEC_RNGIMR */
#define MCF_SEC_RNGIMR_IE               (0x00100000)
#define MCF_SEC_RNGIMR_OFU              (0x02000000)
#define MCF_SEC_RNGIMR_AE               (0x40000000)
#define MCF_SEC_RNGIMR_ME               (0x80000000)

/* Bit definitions and macros for MCF_SEC_AESRCR */
#define MCF_SEC_AESRCR_SR               (0x01000000)
#define MCF_SEC_AESRCR_MI               (0x02000000)
#define MCF_SEC_AESRCR_RI               (0x04000000)

/* Bit definitions and macros for MCF_SEC_AESSR */
#define MCF_SEC_AESSR_RD                (0x01000000)
#define MCF_SEC_AESSR_ID                (0x02000000)
#define MCF_SEC_AESSR_IE                (0x04000000)
#define MCF_SEC_AESSR_OFR               (0x08000000)
#define MCF_SEC_AESSR_IFW               (0x10000000)
#define MCF_SEC_AESSR_HALT              (0x20000000)

/* Bit definitions and macros for MCF_SEC_AESISR */
#define MCF_SEC_AESISR_DSE              (0x00010000)
#define MCF_SEC_AESISR_KSE              (0x00020000)
#define MCF_SEC_AESISR_CE               (0x00040000)
#define MCF_SEC_AESISR_ERE              (0x00080000)
#define MCF_SEC_AESISR_IE               (0x00100000)
#define MCF_SEC_AESISR_OFU              (0x02000000)
#define MCF_SEC_AESISR_IFO              (0x04000000)
#define MCF_SEC_AESISR_IFE              (0x10000000)
#define MCF_SEC_AESISR_OFE              (0x20000000)
#define MCF_SEC_AESISR_AE               (0x40000000)
#define MCF_SEC_AESISR_ME               (0x80000000)

/* Bit definitions and macros for MCF_SEC_AESIMR */
#define MCF_SEC_AESIMR_DSE              (0x00010000)
#define MCF_SEC_AESIMR_KSE              (0x00020000)
#define MCF_SEC_AESIMR_CE               (0x00040000)
#define MCF_SEC_AESIMR_ERE              (0x00080000)
#define MCF_SEC_AESIMR_IE               (0x00100000)
#define MCF_SEC_AESIMR_OFU              (0x02000000)
#define MCF_SEC_AESIMR_IFO              (0x04000000)
#define MCF_SEC_AESIMR_IFE              (0x10000000)
#define MCF_SEC_AESIMR_OFE              (0x20000000)
#define MCF_SEC_AESIMR_AE               (0x40000000)
#define MCF_SEC_AESIMR_ME               (0x80000000)

/********************************************************************/

#endif /* __MCF548X_SEC_H__ */