clk_div5.tan.rpt

比较好的分频代码

; 1.047 ns      ; levelf    ; levelf    ; clk        ; clk      ; 0.000 ns                   ; -0.209 ns                  ; 0.838 ns                 ;
; 1.078 ns      ; countf[2] ; countf[2] ; clk        ; clk      ; 0.000 ns                   ; -0.209 ns                  ; 0.869 ns                 ;
; 1.082 ns      ; countr[2] ; countr[2] ; clk        ; clk      ; 0.000 ns                   ; -0.209 ns                  ; 0.873 ns                 ;
; 1.084 ns      ; countr[2] ; countr[0] ; clk        ; clk      ; 0.000 ns                   ; -0.209 ns                  ; 0.875 ns                 ;
; 1.085 ns      ; countf[2] ; countf[0] ; clk        ; clk      ; 0.000 ns                   ; -0.209 ns                  ; 0.876 ns                 ;
; 1.089 ns      ; countr[2] ; levelr    ; clk        ; clk      ; 0.000 ns                   ; -0.209 ns                  ; 0.880 ns                 ;
; 1.274 ns      ; levelr    ; levelr    ; clk        ; clk      ; 0.000 ns                   ; -0.209 ns                  ; 1.065 ns                 ;
; 1.284 ns      ; countr[0] ; countr[2] ; clk        ; clk      ; 0.000 ns                   ; -0.209 ns                  ; 1.075 ns                 ;
; 1.286 ns      ; countr[0] ; countr[0] ; clk        ; clk      ; 0.000 ns                   ; -0.209 ns                  ; 1.077 ns                 ;
; 1.290 ns      ; countf[1] ; levelf    ; clk        ; clk      ; 0.000 ns                   ; -0.209 ns                  ; 1.081 ns                 ;
; 1.290 ns      ; countf[1] ; countf[1] ; clk        ; clk      ; 0.000 ns                   ; -0.209 ns                  ; 1.081 ns                 ;
; 1.290 ns      ; countf[1] ; countf[0] ; clk        ; clk      ; 0.000 ns                   ; -0.209 ns                  ; 1.081 ns                 ;
; 1.290 ns      ; countf[1] ; countf[2] ; clk        ; clk      ; 0.000 ns                   ; -0.209 ns                  ; 1.081 ns                 ;
; 1.292 ns      ; countr[0] ; countr[1] ; clk        ; clk      ; 0.000 ns                   ; -0.209 ns                  ; 1.083 ns                 ;
; 1.381 ns      ; countr[1] ; levelr    ; clk        ; clk      ; 0.000 ns                   ; -0.209 ns                  ; 1.172 ns                 ;
; 1.381 ns      ; countr[1] ; countr[1] ; clk        ; clk      ; 0.000 ns                   ; -0.209 ns                  ; 1.172 ns                 ;
; 1.381 ns      ; countf[0] ; levelf    ; clk        ; clk      ; 0.000 ns                   ; -0.209 ns                  ; 1.172 ns                 ;
; 1.381 ns      ; countf[0] ; countf[1] ; clk        ; clk      ; 0.000 ns                   ; -0.209 ns                  ; 1.172 ns                 ;
; 1.382 ns      ; countf[0] ; countf[0] ; clk        ; clk      ; 0.000 ns                   ; -0.209 ns                  ; 1.173 ns                 ;
; 1.383 ns      ; countf[0] ; countf[2] ; clk        ; clk      ; 0.000 ns                   ; -0.209 ns                  ; 1.174 ns                 ;
; 1.384 ns      ; countr[1] ; countr[2] ; clk        ; clk      ; 0.000 ns                   ; -0.209 ns                  ; 1.175 ns                 ;
; 1.384 ns      ; countr[1] ; countr[0] ; clk        ; clk      ; 0.000 ns                   ; -0.209 ns                  ; 1.175 ns                 ;
; 1.519 ns      ; countf[2] ; levelf    ; clk        ; clk      ; 0.000 ns                   ; -0.209 ns                  ; 1.310 ns                 ;
; 1.547 ns      ; countr[0] ; levelr    ; clk        ; clk      ; 0.000 ns                   ; -0.209 ns                  ; 1.338 ns                 ;
+---------------+-----------+-----------+------------+----------+----------------------------+----------------------------+--------------------------+


+-------------------------------------------------------------------+
; tco                                                               ;
+-------+--------------+------------+--------+---------+------------+
; Slack ; Required tco ; Actual tco ; From   ; To      ; From Clock ;
+-------+--------------+------------+--------+---------+------------+
; N/A   ; None         ; 7.050 ns   ; levelr ; clk_div ; clk        ;
; N/A   ; None         ; 6.816 ns   ; levelf ; clk_div ; clk        ;
+-------+--------------+------------+--------+---------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Mon May 28 16:37:41 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off clk_div5 -c clk_div5 --timing_analysis_only
Info: Slack time is 48.401 ns for clock "clk" between source register "countr[0]" and destination register "levelr"
    Info: Fmax is restricted to 275.03 MHz due to tcl and tch limits
    Info: + Largest register to register requirement is 49.739 ns
        Info: + Setup relationship between source and destination is 50.000 ns
            Info: + Latch edge is 50.000 ns
                Info: Clock period of Destination clock "clk" is 50.000 ns with  offset of 0.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Destination register is 1
            Info: - Launch edge is 0.000 ns
                Info: Clock period of Source clock "clk" is 50.000 ns with  offset of 0.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Source register is 1
        Info: + Largest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.730 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 8; CLK Node = 'clk'
                Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X1_Y4_N7; Fanout = 2; REG Node = 'levelr'
                Info: Total cell delay = 2.180 ns ( 79.85 % )
                Info: Total interconnect delay = 0.550 ns ( 20.15 % )
            Info: - Longest clock path from clock "clk" to source register is 2.730 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 8; CLK Node = 'clk'
                Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X1_Y4_N2; Fanout = 4; REG Node = 'countr[0]'
                Info: Total cell delay = 2.180 ns ( 79.85 % )
                Info: Total interconnect delay = 0.550 ns ( 20.15 % )
        Info: - Micro clock to output delay of source is 0.224 ns
        Info: - Micro setup delay of destination is 0.037 ns
    Info: - Longest register to register delay is 1.338 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y4_N2; Fanout = 4; REG Node = 'countr[0]'
        Info: 2: + IC(0.600 ns) + CELL(0.738 ns) = 1.338 ns; Loc. = LC_X1_Y4_N7; Fanout = 2; REG Node = 'levelr'
        Info: Total cell delay = 0.738 ns ( 55.16 % )
        Info: Total interconnect delay = 0.600 ns ( 44.84 % )
Info: Minimum slack time is 1.047 ns for clock "clk" between source register "levelf" and destination register "levelf"
    Info: + Shortest register to register delay is 0.838 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y4_N3; Fanout = 2; REG Node = 'levelf'
        Info: 2: + IC(0.529 ns) + CELL(0.309 ns) = 0.838 ns; Loc. = LC_X1_Y4_N3; Fanout = 2; REG Node = 'levelf'
        Info: Total cell delay = 0.309 ns ( 36.87 % )
        Info: Total interconnect delay = 0.529 ns ( 63.13 % )
    Info: - Smallest register to register requirement is -0.209 ns
        Info: + Hold relationship between source and destination is 0.000 ns
            Info: + Latch edge is 25.000 ns
                Info: Clock period of Destination clock "clk" is 50.000 ns with inverted offset of 25.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Destination register is 1
                Info: Multicycle Hold factor for Destination register is 1
            Info: - Launch edge is 25.000 ns
                Info: Clock period of Source clock "clk" is 50.000 ns with inverted offset of 25.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Source register is 1
                Info: Multicycle Hold factor for Source register is 1
        Info: + Smallest clock skew is 0.000 ns
            Info: + Longest clock path from clock "clk" to destination register is 2.730 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 8; CLK Node = 'clk'
                Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X1_Y4_N3; Fanout = 2; REG Node = 'levelf'
                Info: Total cell delay = 2.180 ns ( 79.85 % )
                Info: Total interconnect delay = 0.550 ns ( 20.15 % )
            Info: - Shortest clock path from clock "clk" to source register is 2.730 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 8; CLK Node = 'clk'
                Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X1_Y4_N3; Fanout = 2; REG Node = 'levelf'
                Info: Total cell delay = 2.180 ns ( 79.85 % )
                Info: Total interconnect delay = 0.550 ns ( 20.15 % )
        Info: - Micro clock to output delay of source is 0.224 ns
        Info: + Micro hold delay of destination is 0.015 ns
Info: tco from clock "clk" to destination pin "clk_div" through register "levelr" is 7.050 ns
    Info: + Longest clock path from clock "clk" to source register is 2.730 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 8; CLK Node = 'clk'
        Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X1_Y4_N7; Fanout = 2; REG Node = 'levelr'
        Info: Total cell delay = 2.180 ns ( 79.85 % )
        Info: Total interconnect delay = 0.550 ns ( 20.15 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 4.096 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y4_N7; Fanout = 2; REG Node = 'levelr'
        Info: 2: + IC(0.587 ns) + CELL(0.292 ns) = 0.879 ns; Loc. = LC_X1_Y4_N5; Fanout = 1; COMB Node = 'clk_div~0'
        Info: 3: + IC(1.093 ns) + CELL(2.124 ns) = 4.096 ns; Loc. = PIN_27; Fanout = 0; PIN Node = 'clk_div'
        Info: Total cell delay = 2.416 ns ( 58.98 % )
        Info: Total interconnect delay = 1.680 ns ( 41.02 % )
Info: All timing requirements were met. See Report window for more details.
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
    Info: Processing ended: Mon May 28 16:37:41 2007
    Info: Elapsed time: 00:00:00