clk_div5.vhd

比较好的分频代码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity clk_div5 is
    port(clk:in std_logic;
         clk_div: out std_logic);
end clk_div5;
ARCHITECTURE a OF clk_div5 IS
	constant ld :   STD_LOGIC_VECTOR(2 DOWNTO 0):="010";
	constant md :   STD_LOGIC_VECTOR(2 DOWNTO 0):="100";
	constant zero:   STD_LOGIC_VECTOR(2 DOWNTO 0):=(OTHERS =>'0');
	SIGNAL countr : STD_LOGIC_VECTOR(2 DOWNTO 0);
	SIGNAL countf : STD_LOGIC_VECTOR(2 DOWNTO 0);
	SIGNAL levelr : STD_LOGIC;
	SIGNAL levelf : STD_LOGIC;
BEGIN
    PROCESS (clk)
     begin
      if (clk'event and clk='1') then 
       if (countr = md) then 
        countr <= zero;
       else 
        countr <= countr+1;
       end if ;
      end if ;
    end process;
    PROCESS (clk)
     begin
      if (clk'event and clk='0') then 
       if (countf = md) then 
        countf <= zero;
       else 
        countf <= countf+1;
       end if ;
      end if ;
    end process;
    PROCESS (clk)
     begin
      if (clk'event and clk='1') then 
       if (countr = zero) then 
        levelr <='1';
       elsif (countr = ld) then 
        levelr <='0';
       end if ;
      end if ;
    end process;
    PROCESS (clk)
     begin
      if (clk'event and clk='0') then 
       if (countf = zero) then 
        levelf <='1';
       elsif (countf = ld) then 
        levelf <='0';
       end if ;
      end if ;
    end process;
 clk_div <= levelr or levelf;
END a;