📄 start.s
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;
; file:
; start.S
; description:
; s3c44b0 startup code.
;
; MEMORY AREA
_RAM_STARTADDRESS EQU 0x0c000000
_RAM_ENDADDRESS EQU 0x0c800000
_ROM_STARTADDRESS EQU 0x00000000
_ROM_ENDADDRESS EQU 0x00200000
; STACK DEFINITIONS
_FIQ_STACK_ADDRESS EQU (_RAM_ENDADDRESS-0x00000) ; 14K
_IRQ_STACK_ADDRESS EQU (_RAM_ENDADDRESS-0x03800) ; 14K
_ABT_STACK_ADDRESS EQU (_RAM_ENDADDRESS-0x07000) ; 1K
_SVC_STACK_ADDRESS EQU (_RAM_ENDADDRESS-0x07400) ; 2K
_UND_STACK_ADDRESS EQU (_RAM_ENDADDRESS-0x07c00) ; 1k
_USR_STACK_ADDRESS EQU (_RAM_ENDADDRESS-0x08000) ; 0K
; PROCESSOR MODE
FIQ_MODE EQU 0x11 ; Fast Interrupt Mode (FIQ)
IRQ_MODE EQU 0x12 ; Interrupt Mode (IRQ)
ABT_MODE EQU 0x17 ; Abort Mode(ABT)
SVC_MODE EQU 0x13 ; Supervisor Mode (SVC)
UND_MODE EQU 0x1b ; Undefine Mode(UDF)
USR_MODE EQU 0x10 ; User Mode(USR)
SYS_MODE EQU 0x1f ; System Mode(SYS)
MODE_MSK EQU 0x1f ; Processor Mode Mask
; IRQ BITS
F_BIT EQU 0x40 ; FIQ Disable
I_BIT EQU 0x80 ; IRQ Disable
LOCKOUT EQU 0xc0 ; Interrupt lockout mask value
; WATCHDOG TIMER SPECIAL REGISTERS
WTCON EQU 0x01d30000
WTDAT EQU 0x01d30004
WTCNT EQU 0x01d30008
; INTERRUPT CONTROLLER SPECIAL REGISTERS
INTCON EQU 0x01e00000
INTPND EQU 0x01e00004
INTMOD EQU 0x01e00008
INTMSK EQU 0x01e0000c
I_ISPR EQU 0x01e00020
I_ISPC EQU 0x01e00024
; CPU WRAPPER SPECIAL REGISTERS
SYSCFG EQU 0x01c00000
NCACHBE0 EQU 0x01c00004
NCACHBE1 EQU 0x01c00008
SBUSCON EQU 0x01c40000
; CLOCK GENERATOR & POWER MANAGEMENT SPECIAL REGISTER
PLLCON EQU 0x01d80000
CLKCON EQU 0x01d80004
CLKSLOW EQU 0x01d80008
LOCKTIME EQU 0x01d8000c
M_DIV EQU 56 ; Fin= 8MHz Fout=64MHz
P_DIV EQU 2
S_DIV EQU 1
;M_DIV EQU 52 ; Fin=10MHz Fout=60MHz
;P_DIV EQU 3
;S_DIV EQU 1
; MEMORY CONTROLLER SPECIAL REGISGERS
BWSCON EQU 0x01c80000
BANKCON0 EQU 0x01c80004
BANKCON1 EQU 0x01c80008
BANKCON2 EQU 0x01c8000c
BANKCON3 EQU 0x01c80010
BANKCON4 EQU 0x01c80014
BANKCON5 EQU 0x01c80018
BANKCON6 EQU 0x01c8001c
BANKCON7 EQU 0x01c80020
REFRESH EQU 0x01c80024
BANKSIZE EQU 0x01c80028
MRSRB6 EQU 0x01c8002c
MRSRB7 EQU 0x01c80030
; NON-CACHEABLE AREA CONTROL REGISTER (NCACHBEn)
NCACHESTART EQU 0x00000000 ; Non cache area start adddress 0x00000000
NCACHEEND EQU 0xc0000000 ; Non cache area end address 0x0c000000
; STARTUP CODE
AREA start, CODE, READONLY, ALIGN=4
CODE32
ENTRY
b SystemResetHandler
ldr pc, =_RAM_STARTADDRESS+4 ; b SystemUndefinedHandler
ldr pc, =_RAM_STARTADDRESS+8 ; b SystemSwiHandler
ldr pc, =_RAM_STARTADDRESS+12 ; b SystemPrefetchHandler
ldr pc, =_RAM_STARTADDRESS+16 ; b SystemAbortHandler
ldr pc, =_RAM_STARTADDRESS+20 ; b SystemReservedHandler
ldr pc, =_RAM_STARTADDRESS+24 ; b SystemIrqHandler
ldr pc, =_RAM_STARTADDRESS+28 ; b SystemFiqHandler
LTORG
ConfigMemoryData
DCD 0x11111112 ; BWSCON
DCD 0x00000600 ; GCS0
DCD 0x00007ffc ; GCS1
DCD 0x00007ffc ; GCS2
DCD 0x00007ffc ; GCS3
DCD 0x00007ffc ; GCS4
DCD 0x00007ffc ; GCS5
DCD 0x00018000 ; GCS6, SDRAM (MT = 11, Trcd = 0, SCAN = 0)
DCD 0x00018000 ; GCS7, SDRAM (MT = 11, Trcd = 0, SCAN = 0)
IF M_DIV = 56
DCD 0x00800000+1050
ENDIF
IF M_DIV = 52
DCD 0x00800000+1113
ENDIF
; Refresh(REFEN=1, TREFMD=0, Trp=2, Trc=5, Tchr=3)
; If refresh period is 15.6 us and MCLK is 60 MHz,
; the refresh count is as follows;
; refresh count = 2^11 + 1 - 60x15.6 = 1113
DCD 0x10 ; SCLK power down mode, BankSize 32M/32M
DCD 0x20 ; MRSR 6(CL=2)
DCD 0x20 ; MRSR 7(CL=2)
SystemReservedHandler
b SystemReservedHandler
SystemResetHandler
ldr r0, =WTCON
ldr r1, =0x8000
str r1,[r0]
ldr r0, =INTCON
ldr r1, =0x07
str r1, [r0]
ldr r0, =INTMOD
ldr r1, =0x00
str r1, [r0]
ldr r0, =INTMSK
ldr r1, =0x07ffffff
str r1, [r0]
ldr r0, =I_ISPC
ldr r1, =0x03ffffff
str r1, [r0]
ldr r0, =SYSCFG
ldr r1, =0x00
str r1, [r0]
ldr r0, =NCACHBE0
ldr r1, =NCACHESTART | NCACHEEND
str r1, [r0]
ldr r0, =NCACHBE1
ldr r1, =0x00
str r1, [r0]
b Initialize_Memory
LTORG
Initialize_Memory
mov r0, pc
ldr r1, =_RAM_STARTADDRESS
cmp r0, r1
ldr r0, =ConfigMemoryData
sublt r0, r0, r1
ldmia r0, {r1-r13}
ldr r0, =BWSCON
stmia r0, {r1-r13}
b Initialize_Code
LTORG
IMPORT |Image$$RO$$Base|
IMPORT |Image$$RO$$Limit|
IMPORT |Image$$RW$$Base|
IMPORT |Image$$RW$$Limit|
IMPORT |Image$$ZI$$Base|
IMPORT |Image$$ZI$$Limit|
Initialize_Code
mov r0, pc
ldr r1, =_RAM_STARTADDRESS
cmp r0, r1
bge Initialize_Clock
ldr r0, =_ROM_STARTADDRESS
ldr r1, =|Image$$RO$$Base|
ldr r2, =|Image$$ZI$$Base|
0
cmp r1, r2
bge %F1
ldmia r0!, {r3-r10}
stmia r1!, {r3-r10}
b %B0
1
ldr pc, =_RAM_STARTADDRESS
LTORG
Initialize_Clock
ldr r0, =LOCKTIME
ldr r1, =0x0fff
str r1, [r0]
ldr r0, =PLLCON
ldr r1, =((M_DIV<<12)+(P_DIV<<4)+S_DIV)
str r1, [r0]
ldr r0, =CLKCON
ldr r1, =0x7ff8
str r1,[r0]
b Initialize_Vector
LTORG
Initialize_Vector
ldr r0, =_RAM_STARTADDRESS;
add r0, r0, #4
ldr r1, =SystemUndefinedHandler
sub r1, r1, #8
sub r1, r1, r0
mov r1, r1, lsr#2
orr r1, r1, #0xea000000
str r1, [r0]
add r0, r0, #4
ldr r1, =SystemSwiHandler
sub r1, r1, #8
sub r1, r1, r0
mov r1, r1, lsr#2
orr r1, r1, #0xea000000
str r1, [r0]
add r0, r0, #4
ldr r1, =SystemPrefetchHandler
sub r1, r1, #8
sub r1, r1, r0
mov r1, r1, lsr#2
orr r1, r1, #0xea000000
str r1, [r0]
add r0, r0, #4
ldr r1, =SystemAbortHandler
sub r1, r1, #8
sub r1, r1, r0
mov r1, r1, lsr#2
orr r1, r1, #0xea000000
str r1, [r0]
add r0, r0, #4
ldr r1, =SystemReservedHandler
sub r1, r1, #8
sub r1, r1, r0
mov r1, r1, lsr#2
orr r1, r1, #0xea000000
str r1, [r0]
add r0, r0, #4
ldr r1, =SystemIrqHandler
sub r1, r1, #8
sub r1, r1, r0
mov r1, r1, lsr#2
orr r1, r1, #0xea000000
str r1, [r0]
add r0, r0, #4
ldr r1, =SystemFiqHandler
sub r1, r1, #8
sub r1, r1, r0
mov r1, r1, lsr#2
orr r1, r1, #0xea000000
str r1, [r0]
b Initialize_Stack
LTORG
Initialize_Stack
mov r0, #0x00
orr r1, r0, #LOCKOUT|FIQ_MODE
msr cpsr_cxsf, r1
ldr sp, =_FIQ_STACK_ADDRESS
orr r1, r0, #I_BIT|IRQ_MODE
msr cpsr_cxsf, r1
ldr sp, =_IRQ_STACK_ADDRESS
orr r1, r0, #LOCKOUT|ABT_MODE
msr cpsr_cxsf, r1
ldr sp, =_ABT_STACK_ADDRESS
orr r1, r0, #LOCKOUT|UND_MODE
msr cpsr_cxsf, r1
ldr sp, =_UND_STACK_ADDRESS
orr r1, r0, #LOCKOUT|SVC_MODE
msr cpsr_cxsf, r1
ldr sp, =_SVC_STACK_ADDRESS
b Initialize_Data
LTORG
Initialize_Data
ldr r0, =|Image$$RO$$Limit|
ldr r1, =|Image$$RW$$Base|
ldr r2, =|Image$$ZI$$Base|
ldr r3, =|Image$$ZI$$Limit|
mov r4, #0
cmp r0, r1
beq %F1
0
cmp r1, r2
ldrcc r5, [r0], #4
strcc r5, [r1], #4
bcc %B0
1
cmp r2, r3
strcc r4, [r2], #4
bcc %B1
b Initialize_Entry
LTORG
IMPORT _os_entry
Initialize_Entry
mov r0, #SYS_MODE
msr cpsr_cxsf, r0
ldr sp, =_USR_STACK_ADDRESS
bl _os_entry
b .
LTORG
IMPORT Isr_UndefineHandler
SystemUndefinedHandler
stmfd sp!, {r0-r3, ip, lr}
sub r0, lr, #4
bl Isr_UndefineHandler
ldmfd sp!, {r0-r3, ip, pc}^
IMPORT Isr_SwiHandler
SystemSwiHandler
stmfd sp!, {r0-r3, ip, lr}
sub r0, lr, #4
ldr r1, [r0]
bic r1, r1, #0xff000000
bl Isr_SwiHandler
ldmfd sp!, {r0-r3, ip, pc}^
IMPORT Isr_PrefetchAbortHandler
SystemPrefetchHandler
stmfd sp!, {r0-r3, ip, lr}
sub r0, lr, #4
bl Isr_PrefetchAbortHandler
ldmfd sp!, {r0-r3, ip, lr}
subs pc, lr, #4
IMPORT Isr_DataAbortHandler
SystemAbortHandler
stmfd sp!, {r0-r3, ip, lr}
sub r0, lr, #8
bl Isr_DataAbortHandler
ldmfd sp!, {r0-r3, ip, lr}
subs pc, lr, #8
IMPORT _irq_entry
SystemIrqHandler
stmfd sp!, {r0-r3, ip, lr}
ldr r1, =I_ISPR
ldr r1, [r1]
cmp r1, #0x00 ; If the IDLE mode work-around is used, r1 may be 0 sometimes.
beq %F2
mov r0, #0x00
0
movs r1, r1, lsr #1
bcs %F1
add r0, r0, #1
b %B0
1
mov r2, #1
mov r2, r2, lsl r0
ldr r1, =I_ISPC
str r2, [r1]
b _irq_entry
2
ldmfd sp!, {r0-r3, ip, lr}
subs pc, lr, #4
LTORG
IMPORT _irq_entry
SystemFiqHandler
stmfd sp!, {r0-r3, ip, lr}
ldr r1, =INTPND
ldr r1, [r1]
cmp r1, #0x00 ; If the IDLE mode work-around is used, r1 may be 0 sometimes.
beq %F2
mov r0, #0x00
0
movs r1, r1, lsr #1
bcs %F1
add r0, r0, #1
b %B0
1
mov r2, #1
mov r2, r2, lsl r0
ldr r1, =I_ISPC
str r2, [r1]
b _irq_entry
2
ldmfd sp!, {r0-r3, ip, lr}
subs pc, lr, #4
LTORG
END
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