📄 yunsuanqi.rpt
字号:
65 - - B -- TRI 0 1 0 4 D3
24 - - B -- TRI 0 1 0 4 D4
21 - - B -- TRI 0 1 0 4 D5
22 - - B -- TRI 0 1 0 4 D6
66 - - B -- TRI 0 1 0 4 D7
62 - - C -- OUTPUT 0 1 0 0 seg_a
28 - - C -- OUTPUT 0 1 0 0 seg_b
29 - - C -- OUTPUT 0 1 0 0 seg_c
27 - - C -- OUTPUT 0 1 0 0 seg_d
30 - - C -- OUTPUT 0 1 0 0 seg_e
60 - - C -- OUTPUT 0 1 0 0 seg_f
59 - - C -- OUTPUT 0 1 0 0 seg_g
9 - - - 02 OUTPUT 0 1 0 0 s0
11 - - - 01 OUTPUT 0 1 0 0 s1
23 - - B -- OUTPUT 0 1 0 0 s2
10 - - - 01 OUTPUT 0 1 0 0 s3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\shiyan\maxplus\newyu\yusuan\yunsuanqi.rpt
yunsuanqi
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - C 10 AND2 s 0 2 0 3 |bed_7seg:76|~44~1
- 3 - C 03 AND2 0 3 0 1 |bed_7seg:76|:78
- 1 - C 03 AND2 0 4 0 2 |bed_7seg:76|:87
- 8 - C 06 AND2 0 4 0 1 |bed_7seg:76|:107
- 6 - C 03 AND2 s 0 2 0 1 |bed_7seg:76|~149~1
- 2 - C 06 OR2 0 4 1 0 |bed_7seg:76|:168
- 1 - C 11 OR2 s 0 4 0 1 |bed_7seg:76|~169~1
- 5 - C 06 OR2 s 0 4 0 1 |bed_7seg:76|~169~2
- 5 - C 11 OR2 0 3 1 0 |bed_7seg:76|:169
- 4 - C 10 AND2 0 4 0 1 |bed_7seg:76|:176
- 5 - C 10 OR2 s 0 4 0 1 |bed_7seg:76|~178~1
- 7 - C 06 OR2 s 0 4 0 1 |bed_7seg:76|~178~2
- 5 - C 03 AND2 s 0 3 0 1 |bed_7seg:76|~178~3
- 1 - C 10 OR2 0 4 1 0 |bed_7seg:76|:178
- 3 - C 06 OR2 s 0 4 0 2 |bed_7seg:76|~185~1
- 4 - C 06 OR2 s 0 4 0 1 |bed_7seg:76|~185~2
- 6 - C 06 OR2 s 0 2 0 1 |bed_7seg:76|~185~3
- 1 - C 06 OR2 0 4 1 0 |bed_7seg:76|:185
- 2 - C 03 OR2 s 0 4 0 2 |bed_7seg:76|~186~1
- 8 - C 03 OR2 s 0 4 0 1 |bed_7seg:76|~186~2
- 7 - C 03 OR2 0 4 1 0 |bed_7seg:76|:186
- 4 - C 03 OR2 0 4 1 0 |bed_7seg:76|:187
- 3 - C 10 OR2 s 0 4 0 2 |bed_7seg:76|~188~1
- 6 - C 10 OR2 s 0 4 0 2 |bed_7seg:76|~188~2
- 7 - C 10 OR2 s 0 4 0 1 |bed_7seg:76|~188~3
- 8 - C 10 OR2 0 2 1 0 |bed_7seg:76|:188
- 8 - B 01 DFFE + 1 0 1 9 |cdu16:68|74161:1|f74161:sub|QA (|cdu16:68|74161:1|f74161:sub|:9)
- 6 - B 01 AND2 1 1 0 3 |cdu16:68|74161:1|f74161:sub|:80
- 7 - B 01 DFFE + 0 1 1 10 |cdu16:68|74161:1|f74161:sub|QB (|cdu16:68|74161:1|f74161:sub|:87)
- 4 - B 01 DFFE + 0 2 1 9 |cdu16:68|74161:1|f74161:sub|QC (|cdu16:68|74161:1|f74161:sub|:99)
- 5 - B 01 DFFE + 0 3 1 8 |cdu16:68|74161:1|f74161:sub|QD (|cdu16:68|74161:1|f74161:sub|:110)
- 4 - B 12 DFFE + 0 3 0 3 |cdu16:69|74161:1|f74161:sub|QA (|cdu16:69|74161:1|f74161:sub|:9)
- 7 - B 12 AND2 0 4 0 3 |cdu16:69|74161:1|f74161:sub|:80
- 5 - B 12 DFFE + 0 1 0 4 |cdu16:69|74161:1|f74161:sub|QB (|cdu16:69|74161:1|f74161:sub|:87)
- 8 - B 12 DFFE + 0 2 0 3 |cdu16:69|74161:1|f74161:sub|QC (|cdu16:69|74161:1|f74161:sub|:99)
- 2 - B 12 DFFE + 0 3 0 2 |cdu16:69|74161:1|f74161:sub|QD (|cdu16:69|74161:1|f74161:sub|:110)
- 3 - B 07 DFFE + 1 0 0 4 |cdu16:70|74161:1|f74161:sub|QA (|cdu16:70|74161:1|f74161:sub|:9)
- 2 - B 07 AND2 1 2 0 4 |cdu16:70|74161:1|f74161:sub|:84
- 7 - B 07 DFFE + 1 1 0 3 |cdu16:70|74161:1|f74161:sub|QB (|cdu16:70|74161:1|f74161:sub|:87)
- 6 - B 12 DFFE + 0 1 0 5 |cdu16:70|74161:1|f74161:sub|QC (|cdu16:70|74161:1|f74161:sub|:99)
- 3 - B 12 DFFE + 0 2 0 4 |cdu16:70|74161:1|f74161:sub|QD (|cdu16:70|74161:1|f74161:sub|:110)
- 4 - B 06 OR2 1 2 0 15 |scan:73|74157:1|Y1 (|scan:73|74157:1|:22)
- 1 - B 07 OR2 1 2 0 16 |scan:73|74157:1|Y2 (|scan:73|74157:1|:23)
- 1 - B 12 OR2 1 2 0 18 |scan:73|74157:1|Y3 (|scan:73|74157:1|:24)
- 1 - B 02 OR2 ! 1 2 0 18 |scan:73|74157:1|Y4 (|scan:73|74157:1|:25)
- 1 - B 16 AND2 2 0 0 8 :25
- 1 - B 20 AND2 2 0 0 8 :33
- 5 - B 16 AND2 2 0 0 8 :34
- 2 - B 16 AND2 2 0 0 8 :36
- 3 - B 17 OR2 ! 0 4 0 2 |74181:10|:43
- 3 - B 18 OR2 ! 0 4 0 2 |74181:10|:44
- 3 - B 15 OR2 ! 0 4 0 2 |74181:10|:45
- 4 - B 17 OR2 ! 0 4 0 2 |74181:10|:46
- 5 - B 18 OR2 ! 0 4 0 2 |74181:10|:47
- 2 - B 22 OR2 ! 0 4 0 2 |74181:10|:48
- 2 - B 18 OR2 0 4 0 2 |74181:10|:51
- 1 - B 18 OR2 0 4 0 2 |74181:10|:52
- 1 - B 14 OR2 1 3 0 1 |74181:10|:77
- 6 - B 18 OR2 s 0 3 0 2 |74181:10|CN4~1 (|74181:10|~78~1)
- 1 - B 22 OR2 s 0 3 0 2 |74181:10|CN4~2 (|74181:10|~78~2)
- 6 - B 14 OR2 ! 0 3 0 2 |74181:10|CN4 (|74181:10|:78)
- 2 - B 17 OR2 s 1 2 0 2 |74181:10|~79~1
- 5 - B 17 OR2 s 2 1 0 1 |74181:10|~80~1
- 4 - B 18 OR2 1 3 0 1 |74181:10|:81
- 5 - B 22 OR2 1 3 0 1 |74181:10|:82
- 2 - B 14 OR2 0 4 0 2 |74181:11|:43
- 2 - B 01 OR2 0 4 0 3 |74181:11|:44
- 4 - B 21 OR2 0 4 0 2 |74181:11|:45
- 7 - B 14 OR2 0 4 0 2 |74181:11|:46
- 3 - B 01 OR2 0 4 0 3 |74181:11|:47
- 1 - B 21 OR2 0 4 0 2 |74181:11|:48
- 5 - B 21 OR2 0 4 0 2 |74181:11|:51
- 6 - B 21 OR2 0 4 0 2 |74181:11|:52
- 7 - B 21 OR2 s 0 3 0 2 |74181:11|~74~1
- 1 - B 19 OR2 s 0 3 0 2 |74181:11|~75~1
- 8 - B 21 OR2 1 3 0 1 |74181:11|:77
- 2 - B 21 OR2 0 3 1 0 |74181:11|CN4 (|74181:11|:78)
- 3 - B 14 OR2 s 0 3 0 2 |74181:11|~79~1
- 4 - B 14 OR2 1 1 0 2 |74181:11|:79
- 5 - B 14 OR2 1 3 0 2 |74181:11|:80
- 3 - B 21 OR2 1 3 0 2 |74181:11|:82
- 4 - B 19 OR2 s 0 4 0 1 |74181:11|AEQB~1 (|74181:11|~83~1)
- 1 - B 09 OR2 4 0 0 0 |74244:21|~1~1~2
- 8 - B 06 OR2 s 2 2 0 1 |74244:21|~1~1~3~2
- 1 - B 17 OR2 1 3 1 0 |74244:21|~1~1~3
- 6 - B 17 OR2 1 2 0 1 |74244:21|~1~2
- 4 - B 07 OR2 s 2 2 0 1 |74244:21|~6~1~3~2
- 5 - B 07 OR2 s 1 2 0 1 |74244:21|~6~1~3~3
- 8 - B 07 OR2 1 2 1 0 |74244:21|~6~1~3
- 3 - B 22 OR2 s 2 2 0 1 |74244:21|~10~1~3~2
- 4 - B 22 OR2 s 1 2 0 1 |74244:21|~10~1~3~3
- 6 - B 22 OR2 1 2 1 0 |74244:21|~10~1~3
- 3 - B 16 OR2 s 2 2 0 1 |74244:21|~11~1~3~2
- 8 - B 16 OR2 1 3 1 0 |74244:21|~11~1~3
- 2 - B 19 OR2 s 2 2 0 1 |74244:21|~26~1~3~2
- 3 - B 19 OR2 1 3 1 0 |74244:21|~26~1~3
- 5 - B 19 OR2 1 3 0 1 |74244:21|~26~2
- 4 - B 09 OR2 s 2 2 0 1 |74244:21|~27~1~3~2
- 2 - B 09 OR2 1 3 1 0 |74244:21|~27~1~3
- 3 - B 09 OR2 s 2 2 0 1 |74244:21|~31~1~3~2
- 1 - B 10 OR2 1 3 1 0 |74244:21|~31~1~3
- 6 - B 19 OR2 1 3 0 1 |74244:21|~31~2
- 1 - B 06 OR2 s 2 2 0 1 |74244:21|~36~1~3~2
- 2 - B 06 OR2 s 1 2 0 1 |74244:21|~36~1~3~3
- 6 - B 06 OR2 1 2 1 0 |74244:21|~36~1~3
- 5 - B 15 DFFE 0 2 0 2 |74273:19|Q8 (|74273:19|:12)
- 7 - B 15 DFFE 0 2 0 2 |74273:19|Q7 (|74273:19|:13)
- 1 - B 01 DFFE 0 2 0 2 |74273:19|Q6 (|74273:19|:14)
- 8 - B 14 DFFE 0 2 0 2 |74273:19|Q5 (|74273:19|:15)
- 6 - B 15 DFFE 0 2 0 2 |74273:19|Q4 (|74273:19|:16)
- 2 - B 15 DFFE 0 2 0 2 |74273:19|Q3 (|74273:19|:17)
- 7 - B 18 DFFE 0 2 0 2 |74273:19|Q2 (|74273:19|:18)
- 7 - B 17 DFFE 0 2 0 2 |74273:19|Q1 (|74273:19|:19)
- 8 - B 15 DFFE 0 2 0 2 |74273:20|Q8 (|74273:20|:12)
- 4 - B 20 DFFE 0 2 0 2 |74273:20|Q7 (|74273:20|:13)
- 7 - B 20 DFFE 0 2 0 2 |74273:20|Q6 (|74273:20|:14)
- 3 - B 20 DFFE 0 2 0 2 |74273:20|Q5 (|74273:20|:15)
- 4 - B 15 DFFE 0 2 0 2 |74273:20|Q4 (|74273:20|:16)
- 1 - B 15 DFFE 0 2 0 2 |74273:20|Q3 (|74273:20|:17)
- 8 - B 18 DFFE 0 2 0 2 |74273:20|Q2 (|74273:20|:18)
- 2 - B 20 DFFE 0 2 0 2 |74273:20|Q1 (|74273:20|:19)
- 8 - B 17 DFFE 0 2 0 1 |74374:26|:13
- 6 - B 07 DFFE 0 2 0 1 |74374:26|:14
- 8 - B 22 DFFE 0 2 0 1 |74374:26|:15
- 7 - B 16 DFFE 0 2 0 1 |74374:26|:16
- 5 - B 06 DFFE 0 2 0 1 |74374:26|:17
- 2 - B 10 DFFE 0 2 0 1 |74374:26|:18
- 7 - B 09 DFFE 0 2 0 1 |74374:26|:19
- 8 - B 19 DFFE 0 2 0 1 |74374:26|:20
- 4 - B 16 OR2 1 1 0 1 |74374:26|~43~1
- 5 - B 09 OR2 1 1 0 1 |74374:26|~46~1
- 7 - B 06 DFFE 0 2 0 1 |74374:27|:13
- 1 - B 05 DFFE 0 2 0 1 |74374:27|:14
- 7 - B 22 DFFE 0 2 0 1 |74374:27|:15
- 6 - B 16 DFFE 0 2 0 1 |74374:27|:16
- 3 - B 06 DFFE 0 2 0 1 |74374:27|:17
- 8 - B 09 DFFE 0 2 0 1 |74374:27|:18
- 6 - B 09 DFFE 0 2 0 1 |74374:27|:19
- 7 - B 19 DFFE 0 2 0 1 |74374:27|:20
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\shiyan\maxplus\newyu\yusuan\yunsuanqi.rpt
yunsuanqi
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 36/ 96( 37%) 17/ 48( 35%) 25/ 48( 52%) 0/16( 0%) 1/16( 6%) 8/16( 50%)
C: 4/ 96( 4%) 11/ 48( 22%) 0/ 48( 0%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
02: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\shiyan\maxplus\newyu\yusuan\yunsuanqi.rpt
yunsuanqi
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 12 clk
LCELL 8 :25
LCELL 8 :33
LCELL 8 :34
LCELL 8 :36
Device-Specific Information: e:\shiyan\maxplus\newyu\yusuan\yunsuanqi.rpt
yunsuanqi
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 8 clr
INPUT 4 clr_181
Device-Specific Information: e:\shiyan\maxplus\newyu\yusuan\yunsuanqi.rpt
yunsuanqi
** EQUATIONS **
ALU_BUS : INPUT;
clk : INPUT;
clr : INPUT;
clr_181 : INPUT;
CN : INPUT;
cp_t : INPUT;
encdu : INPUT;
en_181 : INPUT;
LDDR1 : INPUT;
LDDR2 : INPUT;
LDR4 : INPUT;
LDR5 : INPUT;
M : INPUT;
RS_BUS : INPUT;
R4_BUS : INPUT;
scan_clk : INPUT;
SW_BUS : INPUT;
-- Node name is 'CN4'
-- Equation name is 'CN4', type is output
CN4 = _LC2_B21;
-- Node name is 'D0'
-- Equation name is 'D0', type is bidir
D0 = TRI(_LC1_B17, _LC1_B9);
-- Node name is 'D1'
-- Equation name is 'D1', type is bidir
D1 = TRI(_LC8_B7, _LC1_B9);
-- Node name is 'D2'
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -