📄 cunchuqi.rpt
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-- Equation name is '_LC6_C12', type is buried
_LC6_C12 = DFFE( _EQ049, _LC7_C1, GLOBAL( 161clm), VCC, VCC);
_EQ049 = d3 & !161oad
# !_LC5_C12 & _LC6_C12 & 161oad
# _LC5_C12 & !_LC6_C12 & 161oad;
-- Node name is '|74161:26|f74161:sub|:84'
-- Equation name is '_LC7_C12', type is buried
_LC7_C12 = LCELL( _EQ050);
_EQ050 = _LC1_C12 & _LC4_C12;
-- Node name is '|74161:26|f74161:sub|:94'
-- Equation name is '_LC5_C12', type is buried
_LC5_C12 = LCELL( _EQ051);
_EQ051 = _LC1_C12 & _LC2_C12 & _LC4_C12;
-- Node name is '|74161:26|f74161:sub|:104'
-- Equation name is '_LC8_C12', type is buried
_LC8_C12 = LCELL( _EQ052);
_EQ052 = _LC5_C12 & _LC6_C12;
-- Node name is '|74244:25|~1~1~3~2'
-- Equation name is '_LC8_C6', type is buried
-- synthesized logic cell
_LC8_C6 = LCELL( _EQ053);
_EQ053 = pc_bus & sw_bus
# _LC4_C12 & sw_bus
# _LC7_C5 & pc_bus
# _LC4_C12 & _LC7_C5;
-- Node name is '|74244:25|~1~1~3'
-- Equation name is '_LC5_C6', type is buried
_LC5_C6 = LCELL( _EQ054);
_EQ054 = _EC2_C & _LC8_C6
# _LC8_C6 & !memenab
# _LC8_C6 & !rd;
-- Node name is '|74244:25|~6~1~3~2'
-- Equation name is '_LC7_C6', type is buried
-- synthesized logic cell
_LC7_C6 = LCELL( _EQ055);
_EQ055 = pc_bus & sw_bus
# _LC1_C12 & sw_bus
# _LC8_C5 & pc_bus
# _LC1_C12 & _LC8_C5;
-- Node name is '|74244:25|~6~1~3'
-- Equation name is '_LC1_C6', type is buried
_LC1_C6 = LCELL( _EQ056);
_EQ056 = _EC8_C & _LC7_C6
# _LC7_C6 & !memenab
# _LC7_C6 & !rd;
-- Node name is '|74244:25|~10~1~3~2'
-- Equation name is '_LC4_C6', type is buried
-- synthesized logic cell
_LC4_C6 = LCELL( _EQ057);
_EQ057 = pc_bus & sw_bus
# _LC2_C12 & sw_bus
# _LC1_C5 & pc_bus
# _LC1_C5 & _LC2_C12;
-- Node name is '|74244:25|~10~1~3'
-- Equation name is '_LC6_C6', type is buried
_LC6_C6 = LCELL( _EQ058);
_EQ058 = _EC7_C & _LC4_C6
# _LC4_C6 & !memenab
# _LC4_C6 & !rd;
-- Node name is '|74244:25|~11~1~3~2'
-- Equation name is '_LC3_C12', type is buried
-- synthesized logic cell
_LC3_C12 = LCELL( _EQ059);
_EQ059 = pc_bus & sw_bus
# _LC6_C12 & sw_bus
# _LC1_C8 & pc_bus
# _LC1_C8 & _LC6_C12;
-- Node name is '|74244:25|~11~1~3'
-- Equation name is '_LC6_C2', type is buried
_LC6_C2 = LCELL( _EQ060);
_EQ060 = _EC5_C & _LC3_C12
# _LC3_C12 & !memenab
# _LC3_C12 & !rd;
-- Node name is '|74244:25|~26~1~2'
-- Equation name is '_LC4_C2', type is buried
_LC4_C2 = LCELL( _EQ061);
_EQ061 = memenab & rd
# !pc_bus
# !sw_bus;
-- Node name is '|74244:25|~26~1~3~2'
-- Equation name is '_LC8_C2', type is buried
-- synthesized logic cell
_LC8_C2 = LCELL( _EQ062);
_EQ062 = pc_bus & sw_bus
# _LC1_C10 & sw_bus
# _LC4_C8 & pc_bus
# _LC1_C10 & _LC4_C8;
-- Node name is '|74244:25|~26~1~3'
-- Equation name is '_LC3_C2', type is buried
_LC3_C2 = LCELL( _EQ063);
_EQ063 = _EC4_C & _LC8_C2
# _LC8_C2 & !memenab
# _LC8_C2 & !rd;
-- Node name is '|74244:25|~27~1~3~2'
-- Equation name is '_LC4_C10', type is buried
-- synthesized logic cell
_LC4_C10 = LCELL( _EQ064);
_EQ064 = pc_bus & sw_bus
# _LC6_C10 & sw_bus
# _LC2_C8 & pc_bus
# _LC2_C8 & _LC6_C10;
-- Node name is '|74244:25|~27~1~3'
-- Equation name is '_LC3_C6', type is buried
_LC3_C6 = LCELL( _EQ065);
_EQ065 = _EC1_C & _LC4_C10
# _LC4_C10 & !memenab
# _LC4_C10 & !rd;
-- Node name is '|74244:25|~31~1~3~2'
-- Equation name is '_LC1_C2', type is buried
-- synthesized logic cell
_LC1_C2 = LCELL( _EQ066);
_EQ066 = pc_bus & sw_bus
# _LC3_C10 & sw_bus
# _LC3_C8 & pc_bus
# _LC3_C8 & _LC3_C10;
-- Node name is '|74244:25|~31~1~3'
-- Equation name is '_LC5_C2', type is buried
_LC5_C2 = LCELL( _EQ067);
_EQ067 = _EC6_C & _LC1_C2
# _LC1_C2 & !memenab
# _LC1_C2 & !rd;
-- Node name is '|74244:25|~36~1~3~2'
-- Equation name is '_LC7_C2', type is buried
-- synthesized logic cell
_LC7_C2 = LCELL( _EQ068);
_EQ068 = pc_bus & sw_bus
# _LC2_C10 & sw_bus
# _LC5_C8 & pc_bus
# _LC2_C10 & _LC5_C8;
-- Node name is '|74244:25|~36~1~3'
-- Equation name is '_LC2_C2', type is buried
_LC2_C2 = LCELL( _EQ069);
_EQ069 = _EC3_C & _LC7_C2
# _LC7_C2 & !memenab
# _LC7_C2 & !rd;
-- Node name is '|74273:3|:19' = '|74273:3|Q1'
-- Equation name is '_LC8_C3', type is buried
_LC8_C3 = DFFE( d0, _LC3_C3, VCC, VCC, VCC);
-- Node name is '|74273:3|:18' = '|74273:3|Q2'
-- Equation name is '_LC1_C9', type is buried
_LC1_C9 = DFFE( d1, _LC3_C3, VCC, VCC, VCC);
-- Node name is '|74273:3|:17' = '|74273:3|Q3'
-- Equation name is '_LC5_C3', type is buried
_LC5_C3 = DFFE( d2, _LC3_C3, VCC, VCC, VCC);
-- Node name is '|74273:3|:16' = '|74273:3|Q4'
-- Equation name is '_LC7_C3', type is buried
_LC7_C3 = DFFE( d3, _LC3_C3, VCC, VCC, VCC);
-- Node name is '|74273:3|:15' = '|74273:3|Q5'
-- Equation name is '_LC4_C3', type is buried
_LC4_C3 = DFFE( d4, _LC3_C3, VCC, VCC, VCC);
-- Node name is '|74273:3|:14' = '|74273:3|Q6'
-- Equation name is '_LC1_C3', type is buried
_LC1_C3 = DFFE( d5, _LC3_C3, VCC, VCC, VCC);
-- Node name is '|74273:3|:13' = '|74273:3|Q7'
-- Equation name is '_LC2_C3', type is buried
_LC2_C3 = DFFE( d6, _LC3_C3, VCC, VCC, VCC);
-- Node name is '|74273:3|:12' = '|74273:3|Q8'
-- Equation name is '_LC6_C3', type is buried
_LC6_C3 = DFFE( d7, _LC3_C3, VCC, VCC, VCC);
-- Node name is ':13'
-- Equation name is '_LC3_C3', type is buried
_LC3_C3 = LCELL( _EQ070);
_EQ070 = !cp161dar & LDAR;
-- Node name is ':14'
-- Equation name is '_LC7_C1', type is buried
_LC7_C1 = LCELL( _EQ071);
_EQ071 = clk_cdu & 161pc;
-- Node name is '|LPM_RAM_IO:4|altram:sram|segment0_0' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC2_C', type is memory
_EC2_C = MEMORY_SEGMENT( d0, GLOBAL( clk_cdu), VCC, _LC2_C6, VCC, _LC8_C3, _LC1_C9, _LC5_C3, _LC7_C3, _LC4_C3, _LC1_C3, _LC2_C3, _LC6_C3, VCC, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:4|altram:sram|segment0_1' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC8_C', type is memory
_EC8_C = MEMORY_SEGMENT( d1, GLOBAL( clk_cdu), VCC, _LC2_C6, VCC, _LC8_C3, _LC1_C9, _LC5_C3, _LC7_C3, _LC4_C3, _LC1_C3, _LC2_C3, _LC6_C3, VCC, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:4|altram:sram|segment0_2' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC7_C', type is memory
_EC7_C = MEMORY_SEGMENT( d2, GLOBAL( clk_cdu), VCC, _LC2_C6, VCC, _LC8_C3, _LC1_C9, _LC5_C3, _LC7_C3, _LC4_C3, _LC1_C3, _LC2_C3, _LC6_C3, VCC, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:4|altram:sram|segment0_3' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC5_C', type is memory
_EC5_C = MEMORY_SEGMENT( d3, GLOBAL( clk_cdu), VCC, _LC2_C6, VCC, _LC8_C3, _LC1_C9, _LC5_C3, _LC7_C3, _LC4_C3, _LC1_C3, _LC2_C3, _LC6_C3, VCC, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:4|altram:sram|segment0_4' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC3_C', type is memory
_EC3_C = MEMORY_SEGMENT( d4, GLOBAL( clk_cdu), VCC, _LC2_C6, VCC, _LC8_C3, _LC1_C9, _LC5_C3, _LC7_C3, _LC4_C3, _LC1_C3, _LC2_C3, _LC6_C3, VCC, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:4|altram:sram|segment0_5' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC6_C', type is memory
_EC6_C = MEMORY_SEGMENT( d5, GLOBAL( clk_cdu), VCC, _LC2_C6, VCC, _LC8_C3, _LC1_C9, _LC5_C3, _LC7_C3, _LC4_C3, _LC1_C3, _LC2_C3, _LC6_C3, VCC, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:4|altram:sram|segment0_6' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC1_C', type is memory
_EC1_C = MEMORY_SEGMENT( d6, GLOBAL( clk_cdu), VCC, _LC2_C6, VCC, _LC8_C3, _LC1_C9, _LC5_C3, _LC7_C3, _LC4_C3, _LC1_C3, _LC2_C3, _LC6_C3, VCC, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:4|altram:sram|segment0_7' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC4_C', type is memory
_EC4_C = MEMORY_SEGMENT( d7, GLOBAL( clk_cdu), VCC, _LC2_C6, VCC, _LC8_C3, _LC1_C9, _LC5_C3, _LC7_C3, _LC4_C3, _LC1_C3, _LC2_C3, _LC6_C3, VCC, VCC, VCC,);
Project Information e:\shiyan\maxplus\cunchuqi\cunchuqi.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 12,426K
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