📄 cunchuqi.rpt
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Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\shiyan\maxplus\cunchuqi\cunchuqi.rpt
cunchuqi
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - C 21 AND2 s 0 2 0 3 |bed_7seg:38|~67~1
- 7 - C 15 AND2 s 0 2 0 1 |bed_7seg:38|~87~1
- 6 - C 21 AND2 0 4 0 1 |bed_7seg:38|:87
- 4 - C 14 AND2 0 3 0 1 |bed_7seg:38|:107
- 7 - C 14 AND2 s 0 3 0 1 |bed_7seg:38|~168~1
- 2 - C 14 OR2 0 4 1 0 |bed_7seg:38|:168
- 3 - C 14 OR2 s 0 4 0 1 |bed_7seg:38|~169~1
- 1 - C 14 OR2 0 4 1 0 |bed_7seg:38|:169
- 5 - C 15 OR2 s 0 4 0 2 |bed_7seg:38|~178~1
- 7 - C 21 OR2 s 0 4 0 1 |bed_7seg:38|~178~2
- 3 - C 15 OR2 0 4 1 0 |bed_7seg:38|:178
- 5 - C 21 AND2 0 3 0 2 |bed_7seg:38|:184
- 6 - C 15 OR2 s 0 4 0 2 |bed_7seg:38|~185~1
- 8 - C 15 OR2 s 0 4 0 1 |bed_7seg:38|~185~2
- 8 - C 21 AND2 s 0 3 0 1 |bed_7seg:38|~185~3
- 2 - C 15 OR2 0 3 1 0 |bed_7seg:38|:185
- 2 - C 21 OR2 0 4 1 0 |bed_7seg:38|:186
- 4 - C 15 OR2 s 0 4 0 2 |bed_7seg:38|~187~1
- 3 - C 21 OR2 s 0 4 0 2 |bed_7seg:38|~187~2
- 4 - C 21 OR2 0 4 1 0 |bed_7seg:38|:187
- 5 - C 14 OR2 s 0 4 0 1 |bed_7seg:38|~188~1
- 6 - C 14 OR2 s 0 2 0 1 |bed_7seg:38|~188~2
- 1 - C 15 OR2 0 4 1 0 |bed_7seg:38|:188
- 5 - C 08 DFFE + 0 3 0 3 |cdu16:39|74161:1|f74161:sub|QA (|cdu16:39|74161:1|f74161:sub|:9)
- 7 - C 08 AND2 0 4 0 3 |cdu16:39|74161:1|f74161:sub|:80
- 3 - C 08 DFFE + 0 1 0 4 |cdu16:39|74161:1|f74161:sub|QB (|cdu16:39|74161:1|f74161:sub|:87)
- 2 - C 08 DFFE + 0 2 0 3 |cdu16:39|74161:1|f74161:sub|QC (|cdu16:39|74161:1|f74161:sub|:99)
- 4 - C 08 DFFE + 0 3 0 2 |cdu16:39|74161:1|f74161:sub|QD (|cdu16:39|74161:1|f74161:sub|:110)
- 7 - C 05 DFFE + 1 0 0 5 |cdu16:49|74161:1|f74161:sub|QA (|cdu16:49|74161:1|f74161:sub|:9)
- 2 - C 05 AND2 1 2 0 3 |cdu16:49|74161:1|f74161:sub|:84
- 8 - C 05 DFFE + 1 1 0 4 |cdu16:49|74161:1|f74161:sub|QB (|cdu16:49|74161:1|f74161:sub|:87)
- 1 - C 05 DFFE + 1 2 0 5 |cdu16:49|74161:1|f74161:sub|QC (|cdu16:49|74161:1|f74161:sub|:99)
- 1 - C 08 DFFE + 0 2 0 4 |cdu16:49|74161:1|f74161:sub|QD (|cdu16:49|74161:1|f74161:sub|:110)
- 4 - C 05 LCELL s 1 0 1 0 GW~1
- - 2 C -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:4|altram:sram|segment0_0
- - 8 C -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:4|altram:sram|segment0_1
- - 7 C -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:4|altram:sram|segment0_2
- - 5 C -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:4|altram:sram|segment0_3
- - 3 C -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:4|altram:sram|segment0_4
- - 6 C -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:4|altram:sram|segment0_5
- - 1 C -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:4|altram:sram|segment0_6
- - 4 C -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:4|altram:sram|segment0_7
- 2 - C 06 AND2 3 0 0 8 |LPM_RAM_IO:4|:91
- 6 - C 05 OR2 1 2 0 13 |scan:42|74157:1|Y1 (|scan:42|74157:1|:22)
- 5 - C 05 OR2 ! 1 2 0 13 |scan:42|74157:1|Y2 (|scan:42|74157:1|:23)
- 6 - C 08 OR2 ! 1 2 0 16 |scan:42|74157:1|Y3 (|scan:42|74157:1|:24)
- 8 - C 08 OR2 ! 1 2 0 16 |scan:42|74157:1|Y4 (|scan:42|74157:1|:25)
- 3 - C 05 LCELL s 1 0 1 0 SW~1
- 3 - C 03 AND2 2 0 0 8 :13
- 7 - C 01 AND2 2 0 0 8 :14
- 2 - C 10 DFFE 1 3 0 4 |74161:1|f74161:sub|QA (|74161:1|f74161:sub|:9)
- 7 - C 10 AND2 0 2 0 1 |74161:1|f74161:sub|:80
- 5 - C 10 AND2 0 3 0 1 |74161:1|f74161:sub|:84
- 3 - C 10 DFFE 1 3 0 3 |74161:1|f74161:sub|QB (|74161:1|f74161:sub|:87)
- 8 - C 10 AND2 0 4 0 1 |74161:1|f74161:sub|:94
- 6 - C 10 DFFE 1 3 0 2 |74161:1|f74161:sub|QC (|74161:1|f74161:sub|:99)
- 1 - C 10 DFFE 1 3 0 1 |74161:1|f74161:sub|QD (|74161:1|f74161:sub|:110)
- 4 - C 12 DFFE 1 2 0 4 |74161:26|f74161:sub|QA (|74161:26|f74161:sub|:9)
- 7 - C 12 AND2 0 2 0 1 |74161:26|f74161:sub|:84
- 1 - C 12 DFFE 1 3 0 3 |74161:26|f74161:sub|QB (|74161:26|f74161:sub|:87)
- 5 - C 12 AND2 0 3 0 2 |74161:26|f74161:sub|:94
- 2 - C 12 DFFE 1 3 0 2 |74161:26|f74161:sub|QC (|74161:26|f74161:sub|:99)
- 8 - C 12 AND2 0 2 0 4 |74161:26|f74161:sub|:104
- 6 - C 12 DFFE 1 3 0 2 |74161:26|f74161:sub|QD (|74161:26|f74161:sub|:110)
- 8 - C 06 OR2 s 2 2 0 1 |74244:25|~1~1~3~2
- 5 - C 06 OR2 2 2 1 0 |74244:25|~1~1~3
- 7 - C 06 OR2 s 2 2 0 1 |74244:25|~6~1~3~2
- 1 - C 06 OR2 2 2 1 0 |74244:25|~6~1~3
- 4 - C 06 OR2 s 2 2 0 1 |74244:25|~10~1~3~2
- 6 - C 06 OR2 2 2 1 0 |74244:25|~10~1~3
- 3 - C 12 OR2 s 2 2 0 1 |74244:25|~11~1~3~2
- 6 - C 02 OR2 2 2 1 0 |74244:25|~11~1~3
- 4 - C 02 OR2 4 0 0 0 |74244:25|~26~1~2
- 8 - C 02 OR2 s 2 2 0 1 |74244:25|~26~1~3~2
- 3 - C 02 OR2 2 2 1 0 |74244:25|~26~1~3
- 4 - C 10 OR2 s 2 2 0 1 |74244:25|~27~1~3~2
- 3 - C 06 OR2 2 2 1 0 |74244:25|~27~1~3
- 1 - C 02 OR2 s 2 2 0 1 |74244:25|~31~1~3~2
- 5 - C 02 OR2 2 2 1 0 |74244:25|~31~1~3
- 7 - C 02 OR2 s 2 2 0 1 |74244:25|~36~1~3~2
- 2 - C 02 OR2 2 2 1 0 |74244:25|~36~1~3
- 6 - C 03 DFFE 0 2 1 8 |74273:3|Q8 (|74273:3|:12)
- 2 - C 03 DFFE 0 2 1 8 |74273:3|Q7 (|74273:3|:13)
- 1 - C 03 DFFE 0 2 1 8 |74273:3|Q6 (|74273:3|:14)
- 4 - C 03 DFFE 0 2 1 8 |74273:3|Q5 (|74273:3|:15)
- 7 - C 03 DFFE 0 2 1 8 |74273:3|Q4 (|74273:3|:16)
- 5 - C 03 DFFE 0 2 1 8 |74273:3|Q3 (|74273:3|:17)
- 1 - C 09 DFFE 0 2 1 8 |74273:3|Q2 (|74273:3|:18)
- 8 - C 03 DFFE 0 2 1 8 |74273:3|Q1 (|74273:3|:19)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\shiyan\maxplus\cunchuqi\cunchuqi.rpt
cunchuqi
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 1/ 48( 2%) 1/ 48( 2%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
B: 0/ 96( 0%) 3/ 48( 6%) 0/ 48( 0%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
C: 35/ 96( 36%) 30/ 48( 62%) 3/ 48( 6%) 2/16( 12%) 1/16( 6%) 6/16( 37%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 3/24( 12%) 1/4( 25%) 0/4( 0%) 1/4( 25%)
02: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
03: 5/24( 20%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 2/24( 8%) 0/4( 0%) 0/4( 0%) 1/4( 25%)
07: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\shiyan\maxplus\cunchuqi\cunchuqi.rpt
cunchuqi
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 8 en_cdu
LCELL 8 :13
LCELL 8 :14
Device-Specific Information: e:\shiyan\maxplus\cunchuqi\cunchuqi.rpt
cunchuqi
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 8 clr_cdu
INPUT 8 161clm
Device-Specific Information: e:\shiyan\maxplus\cunchuqi\cunchuqi.rpt
cunchuqi
** EQUATIONS **
clk_cdu : INPUT;
clr_cdu : INPUT;
cp161dar : INPUT;
en_cdu : INPUT;
LDAR : INPUT;
memenab : INPUT;
pc_bus : INPUT;
rd : INPUT;
scan_clk : INPUT;
sw_bus : INPUT;
we : INPUT;
161clm : INPUT;
161oad : INPUT;
161pc : INPUT;
-- Node name is 'adr0'
-- Equation name is 'adr0', type is output
adr0 = _LC8_C3;
-- Node name is 'adr1'
-- Equation name is 'adr1', type is output
adr1 = _LC1_C9;
-- Node name is 'adr2'
-- Equation name is 'adr2', type is output
adr2 = _LC5_C3;
-- Node name is 'adr3'
-- Equation name is 'adr3', type is output
adr3 = _LC7_C3;
-- Node name is 'adr4'
-- Equation name is 'adr4', type is output
adr4 = _LC4_C3;
-- Node name is 'adr5'
-- Equation name is 'adr5', type is output
adr5 = _LC1_C3;
-- Node name is 'adr6'
-- Equation name is 'adr6', type is output
adr6 = _LC2_C3;
-- Node name is 'adr7'
-- Equation name is 'adr7', type is output
adr7 = _LC6_C3;
-- Node name is 'd0'
-- Equation name is 'd0', type is bidir
d0 = TRI(_LC5_C6, _LC4_C2);
-- Node name is 'd1'
-- Equation name is 'd1', type is bidir
d1 = TRI(_LC1_C6, _LC4_C2);
-- Node name is 'd2'
-- Equation name is 'd2', type is bidir
d2 = TRI(_LC6_C6, _LC4_C2);
-- Node name is 'd3'
-- Equation name is 'd3', type is bidir
d3 = TRI(_LC6_C2, _LC4_C2);
-- Node name is 'd4'
-- Equation name is 'd4', type is bidir
d4 = TRI(_LC2_C2, _LC4_C2);
-- Node name is 'd5'
-- Equation name is 'd5', type is bidir
d5 = TRI(_LC5_C2, _LC4_C2);
-- Node name is 'd6'
-- Equation name is 'd6', type is bidir
d6 = TRI(_LC3_C6, _LC4_C2);
-- Node name is 'd7'
-- Equation name is 'd7', type is bidir
d7 = TRI(_LC3_C2, _LC4_C2);
-- Node name is 'GW'
-- Equation name is 'GW', type is output
GW = !_LC4_C5;
-- Node name is 'GW~1'
-- Equation name is 'GW~1', location is LC4_C5, type is buried.
-- synthesized logic cell
_LC4_C5 = LCELL( scan_clk);
-- Node name is 'seg_a'
-- Equation name is 'seg_a', type is output
seg_a = _LC2_C15;
-- Node name is 'seg_b'
-- Equation name is 'seg_b', type is output
seg_b = _LC2_C14;
-- Node name is 'seg_c'
-- Equation name is 'seg_c', type is output
seg_c = _LC1_C14;
-- Node name is 'seg_d'
-- Equation name is 'seg_d', type is output
seg_d = _LC3_C15;
-- Node name is 'seg_e'
-- Equation name is 'seg_e', type is output
seg_e = _LC2_C21;
-- Node name is 'seg_f'
-- Equation name is 'seg_f', type is output
seg_f = _LC4_C21;
-- Node name is 'seg_g'
-- Equation name is 'seg_g', type is output
seg_g = _LC1_C15;
-- Node name is 'SW'
-- Equation name is 'SW', type is output
SW = _LC3_C5;
-- Node name is 'SW~1'
-- Equation name is 'SW~1', location is LC3_C5, type is buried.
-- synthesized logic cell
_LC3_C5 = LCELL( scan_clk);
-- Node name is '|bed_7seg:38|~67~1' from file "bed_7seg.tdf" line 10, column 8
-- Equation name is '_LC1_C21', type is buried
-- synthesized logic cell
_LC1_C21 = LCELL( _EQ001);
_EQ001 = _LC5_C5 & _LC6_C5;
-- Node name is '|bed_7seg:38|~87~1' from file "bed_7seg.tdf" line 12, column 8
-- Equation name is '_LC7_C15', type is buried
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