wyyunsuanqi.rpt

maxplus下连接硬件实现74181运算器

F:       9/ 96(  9%)     0/ 48(  0%)     1/ 48(  2%)    4/16( 25%)      0/16(  0%)     3/16( 18%)


Column FastTrack Interconnect:

         FastTrack                                 
Column  Interconnect    Input Pins     Output Pins     Bidir Pins
01:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
02:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
03:      2/24(  8%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
04:      1/24(  4%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
05:      3/24( 12%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
06:      2/24(  8%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
07:      1/24(  4%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
08:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
09:      1/24(  4%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
10:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
11:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
12:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
13:      4/24( 16%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
14:      3/24( 12%)     0/4(  0%)      2/4( 50%)       0/4(  0%)
15:      2/24(  8%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
16:      2/24(  8%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
17:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
18:      4/24( 16%)     0/4(  0%)      2/4( 50%)       0/4(  0%)
19:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
20:      3/24( 12%)     0/4(  0%)      0/4(  0%)       1/4( 25%)
21:      4/24( 16%)     0/4(  0%)      0/4(  0%)       1/4( 25%)
22:      3/24( 12%)     0/4(  0%)      0/4(  0%)       1/4( 25%)
23:      3/24( 12%)     0/4(  0%)      0/4(  0%)       1/4( 25%)
24:      2/24(  8%)     0/4(  0%)      0/4(  0%)       1/4( 25%)
EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:        e:\program\edamaxplus\exm3\wyyunsuanqi.rpt
wyyunsuanqi

** CLOCK SIGNALS **

Type     Fan-out       Name
INPUT       12         clk
LCELL        8         :21
LCELL        8         :24
LCELL        8         :30
LCELL        8         :46
INPUT        2         scan_clk


Device-Specific Information:        e:\program\edamaxplus\exm3\wyyunsuanqi.rpt
wyyunsuanqi

** CLEAR SIGNALS **

Type     Fan-out       Name
INPUT        8         clr
INPUT        4         clr_181


Device-Specific Information:        e:\program\edamaxplus\exm3\wyyunsuanqi.rpt
wyyunsuanqi

** EQUATIONS **

alu_bus  : INPUT;
clk      : INPUT;
clr      : INPUT;
clr_181  : INPUT;
cn       : INPUT;
cp_t     : INPUT;
encdu    : INPUT;
en_181   : INPUT;
lddr1    : INPUT;
lddr2    : INPUT;
ldr4     : INPUT;
ldr5     : INPUT;
m        : INPUT;
r4_bus   : INPUT;
r5_bus   : INPUT;
scan_clk : INPUT;
sw_bus   : INPUT;

-- Node name is 'cn4' 
-- Equation name is 'cn4', type is output 
cn4      =  _LC6_B19;

-- Node name is 'd0' 
-- Equation name is 'd0', type is bidir 
d0       = TRI(_LC2_B10,  _LC1_B19);

-- Node name is 'd1' 
-- Equation name is 'd1', type is bidir 
d1       = TRI(_LC5_B6,  _LC1_B19);

-- Node name is 'd2' 
-- Equation name is 'd2', type is bidir 
d2       = TRI(_LC6_B20,  _LC1_B19);

-- Node name is 'd3' 
-- Equation name is 'd3', type is bidir 
d3       = TRI(_LC8_B23,  _LC1_B19);

-- Node name is 'd4' 
-- Equation name is 'd4', type is bidir 
d4       = TRI(_LC1_B24,  _LC1_B19);

-- Node name is 'd5' 
-- Equation name is 'd5', type is bidir 
d5       = TRI(_LC5_B21,  _LC1_B19);

-- Node name is 'd6' 
-- Equation name is 'd6', type is bidir 
d6       = TRI(_LC2_B22,  _LC1_B19);

-- Node name is 'd7' 
-- Equation name is 'd7', type is bidir 
d7       = TRI(_LC4_B19,  _LC1_B19);

-- Node name is 'gw' 
-- Equation name is 'gw', type is output 
gw       =  _LC8_B3;

-- Node name is 'seg_a' 
-- Equation name is 'seg_a', type is output 
seg_a    =  _LC8_B14;

-- Node name is 'seg_b' 
-- Equation name is 'seg_b', type is output 
seg_b    =  _LC4_B14;

-- Node name is 'seg_c' 
-- Equation name is 'seg_c', type is output 
seg_c    =  _LC1_B15;

-- Node name is 'seg_d' 
-- Equation name is 'seg_d', type is output 
seg_d    =  _LC4_B15;

-- Node name is 'seg_e' 
-- Equation name is 'seg_e', type is output 
seg_e    =  _LC8_B18;

-- Node name is 'seg_f' 
-- Equation name is 'seg_f', type is output 
seg_f    =  _LC7_B18;

-- Node name is 'seg_g' 
-- Equation name is 'seg_g', type is output 
seg_g    =  _LC6_B18;

-- Node name is 'sw' 
-- Equation name is 'sw', type is output 
sw       = !_LC2_A10;

-- Node name is 's0' 
-- Equation name is 's0', type is output 
s0       =  _LC4_B5;

-- Node name is 's1' 
-- Equation name is 's1', type is output 
s1       =  _LC5_B5;

-- Node name is 's2' 
-- Equation name is 's2', type is output 
s2       =  _LC2_B5;

-- Node name is 's3' 
-- Equation name is 's3', type is output 
s3       =  _LC3_B5;

-- Node name is '|wybed_7seg:51|:58' from file "wybed_7seg.tdf" line 9, column 8
-- Equation name is '_LC6_B14', type is buried 
_LC6_B14 = LCELL( _EQ001);
  _EQ001 = !_LC1_B3 & !_LC1_B10 &  _LC5_B14 & !_LC5_B17;

-- Node name is '|wybed_7seg:51|:67' from file "wybed_7seg.tdf" line 10, column 8
-- Equation name is '_LC2_B14', type is buried 
_LC2_B14 = LCELL( _EQ002);
  _EQ002 = !_LC1_B3 &  _LC1_B10 &  _LC5_B14 & !_LC5_B17;

-- Node name is '|wybed_7seg:51|~78~1' from file "wybed_7seg.tdf" line 11, column 8
-- Equation name is '_LC3_B14', type is buried 
-- synthesized logic cell 
_LC3_B14 = LCELL( _EQ003);
  _EQ003 = !_LC1_B10 & !_LC5_B14;

-- Node name is '|wybed_7seg:51|:107' from file "wybed_7seg.tdf" line 14, column 8
-- Equation name is '_LC7_B14', type is buried 
_LC7_B14 = LCELL( _EQ004);
  _EQ004 = !_LC1_B3 &  _LC1_B10 &  _LC5_B14 &  _LC5_B17;

-- Node name is '|wybed_7seg:51|:168' from file "wybed_7seg.tdf" line 20, column 18
-- Equation name is '_LC4_B14', type is buried 
_LC4_B14 = LCELL( _EQ005);
  _EQ005 = !_LC1_B3 & !_LC1_B10 & !_LC5_B14
         # !_LC5_B14 & !_LC5_B17
         # !_LC1_B10 & !_LC5_B17
         #  _LC1_B3 &  _LC1_B10 & !_LC5_B14
         # !_LC1_B3 &  _LC1_B10 &  _LC5_B14;

-- Node name is '|wybed_7seg:51|:169' from file "wybed_7seg.tdf" line 20, column 20
-- Equation name is '_LC1_B15', type is buried 
_LC1_B15 = LCELL( _EQ006);
  _EQ006 =  _LC1_B10 & !_LC5_B17
         #  _LC1_B3 & !_LC5_B17
         # !_LC5_B14 & !_LC5_B17
         # !_LC1_B3 &  _LC5_B17
         #  _LC1_B10 & !_LC5_B14;

-- Node name is '|wybed_7seg:51|:178' from file "wybed_7seg.tdf" line 21, column 22
-- Equation name is '_LC4_B15', type is buried 
_LC4_B15 = LCELL( _EQ007);
  _EQ007 =  _LC1_B18
         #  _LC3_B14 & !_LC5_B17
         #  _LC1_B3 &  _LC3_B14;

-- Node name is '|wybed_7seg:51|:185' from file "wybed_7seg.tdf" line 22, column 16
-- Equation name is '_LC8_B14', type is buried 
_LC8_B14 = LCELL( _EQ008);
  _EQ008 =  _LC1_B14
         #  _LC6_B14
         #  _LC2_B14
         #  _LC7_B14;

-- Node name is '|wybed_7seg:51|~186~1' from file "wybed_7seg.tdf" line 22, column 24
-- Equation name is '_LC3_B18', type is buried 
-- synthesized logic cell 
_LC3_B18 = LCELL( _EQ009);
  _EQ009 =  _LC1_B3 &  _LC1_B10 & !_LC5_B14 &  _LC5_B17
         #  _LC1_B3 &  _LC1_B10 &  _LC5_B14 & !_LC5_B17;

-- Node name is '|wybed_7seg:51|:186' from file "wybed_7seg.tdf" line 22, column 24
-- Equation name is '_LC8_B18', type is buried 
_LC8_B18 = LCELL( _EQ010);
  _EQ010 =  _LC2_B18
         #  _LC3_B18
         #  _LC6_B14;

-- Node name is '|wybed_7seg:51|~187~1' from file "wybed_7seg.tdf" line 22, column 26
-- Equation name is '_LC1_B14', type is buried 
-- synthesized logic cell 
_LC1_B14 = LCELL( _EQ011);
  _EQ011 = !_LC1_B3 &  _LC1_B10 & !_LC5_B14 &  _LC5_B17
         #  _LC1_B3 & !_LC5_B14 & !_LC5_B17
         # !_LC1_B10 & !_LC5_B14 & !_LC5_B17
         #  _LC1_B3 &  _LC5_B14 &  _LC5_B17
         # !_LC1_B10 &  _LC5_B14 &  _LC5_B17
         #  _LC1_B3 & !_LC1_B10;

-- Node name is '|wybed_7seg:51|~187~2' from file "wybed_7seg.tdf" line 22, column 26
-- Equation name is '_LC2_B18', type is buried 
-- synthesized logic cell 
_LC2_B18 = LCELL( _EQ012);
  _EQ012 = !_LC1_B10 & !_LC5_B14 & !_LC5_B17
         #  _LC1_B3 &  _LC5_B14 &  _LC5_B17
         # !_LC1_B10 &  _LC5_B14 &  _LC5_B17
         #  _LC1_B3 & !_LC1_B10;

-- Node name is '|wybed_7seg:51|~187~3' from file "wybed_7seg.tdf" line 22, column 26
-- Equation name is '_LC4_B18', type is buried 
-- synthesized logic cell 
_LC4_B18 = LCELL( _EQ013);
  _EQ013 = !_LC1_B3 & !_LC1_B10 & !_LC5_B14 &  _LC5_B17
         #  _LC1_B3 &  _LC1_B10 &  _LC5_B14 & !_LC5_B17;

-- Node name is '|wybed_7seg:51|:187' from file "wybed_7seg.tdf" line 22, column 26
-- Equation name is '_LC7_B18', type is buried 
_LC7_B18 = LCELL( _EQ014);
  _EQ014 =  _LC4_B18
         #  _LC1_B14;

-- Node name is '|wybed_7seg:51|~188~1' from file "wybed_7seg.tdf" line 22, column 28
-- Equation name is '_LC1_B18', type is buried 
-- synthesized logic cell 
_LC1_B18 = LCELL( _EQ015);
  _EQ015 = !_LC1_B3 & !_LC1_B10 &  _LC5_B14
         #  _LC1_B10 & !_LC5_B14 &  _LC5_B17
         # !_LC1_B10 &  _LC5_B14 &  _LC5_B17
         #  _LC1_B3 &  _LC1_B10 & !_LC5_B14
         # !_LC1_B3 &  _LC5_B14 & !_LC5_B17
         #  _LC1_B3 &  _LC1_B10 & !_LC5_B17;

-- Node name is '|wybed_7seg:51|~188~2' from file "wybed_7seg.tdf" line 22, column 28
-- Equation name is '_LC5_B18', type is buried 
-- synthesized logic cell 
_LC5_B18 = LCELL( _EQ016);
  _EQ016 =  _LC1_B3 & !_LC1_B10 & !_LC5_B17
         # !_LC1_B3 & !_LC1_B10 & !_LC5_B14 &  _LC5_B17
         #  _LC1_B3 &  _LC1_B10 &  _LC5_B14 &  _LC5_B17;