📄 wyyunsuanqi.rpt
字号:
Total output pins required: 14
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 8
Total reserved pins required 0
Total logic cells required: 131
Total flipflops required: 46
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 27/1152 ( 2%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1/0
B: 3 0 2 1 8 7 0 0 8 7 0 7 0 8 8 2 8 8 8 8 7 6 8 8 8 130/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 3 0 2 1 8 7 0 0 8 8 0 7 0 8 8 2 8 8 8 8 7 6 8 8 8 131/0
Device-Specific Information: e:\program\edamaxplus\exm3\wyyunsuanqi.rpt
wyyunsuanqi
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
82 - - E -- INPUT 0 0 0 9 alu_bus
122 - - - 13 INPUT 0 0 0 12 clk
95 - - B -- INPUT 0 0 0 8 clr
79 - - F -- INPUT 0 0 0 4 clr_181
73 - - - 01 INPUT 0 0 0 2 cn
128 - - - 13 INPUT 0 0 0 4 cp_t
31 - - F -- BIDIR 0 1 0 4 d0
32 - - F -- BIDIR 0 1 0 4 d1
33 - - F -- BIDIR 0 1 0 4 d2
36 - - - 24 BIDIR 0 1 0 4 d3
37 - - - 23 BIDIR 0 1 0 4 d4
38 - - - 22 BIDIR 0 1 0 4 d5
39 - - - 21 BIDIR 0 1 0 4 d6
41 - - - 20 BIDIR 0 1 0 4 d7
92 - - C -- INPUT 0 0 0 3 encdu
78 - - F -- INPUT 0 0 0 2 en_181
88 - - D -- INPUT 0 0 0 1 lddr1
89 - - C -- INPUT 0 0 0 1 lddr2
86 - - E -- INPUT 0 0 0 1 ldr4
87 - - E -- INPUT 0 0 0 1 ldr5
72 - - - 03 INPUT 0 0 0 8 m
80 - - F -- INPUT 0 0 0 9 r4_bus
81 - - F -- INPUT 0 0 0 9 r5_bus
125 - - - -- INPUT G 0 0 0 0 scan_clk
83 - - E -- INPUT 0 0 0 9 sw_bus
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\program\edamaxplus\exm3\wyyunsuanqi.rpt
wyyunsuanqi
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
96 - - B -- OUTPUT 0 1 0 0 cn4
31 - - F -- TRI 0 1 0 4 d0
32 - - F -- TRI 0 1 0 4 d1
33 - - F -- TRI 0 1 0 4 d2
36 - - - 24 TRI 0 1 0 4 d3
37 - - - 23 TRI 0 1 0 4 d4
38 - - - 22 TRI 0 1 0 4 d5
39 - - - 21 TRI 0 1 0 4 d6
41 - - - 20 TRI 0 1 0 4 d7
8 - - A -- OUTPUT 0 1 0 0 gw
51 - - - 14 OUTPUT 0 1 0 0 seg_a
49 - - - 14 OUTPUT 0 1 0 0 seg_b
48 - - - 15 OUTPUT 0 1 0 0 seg_c
47 - - - 16 OUTPUT 0 1 0 0 seg_d
46 - - - 17 OUTPUT 0 1 0 0 seg_e
44 - - - 18 OUTPUT 0 1 0 0 seg_f
43 - - - 18 OUTPUT 0 1 0 0 seg_g
102 - - A -- OUTPUT 0 1 0 0 sw
9 - - B -- OUTPUT 0 1 0 0 s0
10 - - B -- OUTPUT 0 1 0 0 s1
12 - - C -- OUTPUT 0 1 0 0 s2
13 - - C -- OUTPUT 0 1 0 0 s3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\program\edamaxplus\exm3\wyyunsuanqi.rpt
wyyunsuanqi
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - B 14 AND2 0 4 0 2 |wybed_7seg:51|:58
- 2 - B 14 AND2 0 4 0 1 |wybed_7seg:51|:67
- 3 - B 14 AND2 s 0 2 0 1 |wybed_7seg:51|~78~1
- 7 - B 14 AND2 0 4 0 1 |wybed_7seg:51|:107
- 4 - B 14 OR2 0 4 1 0 |wybed_7seg:51|:168
- 1 - B 15 OR2 0 4 1 0 |wybed_7seg:51|:169
- 4 - B 15 OR2 0 4 1 0 |wybed_7seg:51|:178
- 8 - B 14 OR2 0 4 1 0 |wybed_7seg:51|:185
- 3 - B 18 OR2 s 0 4 0 1 |wybed_7seg:51|~186~1
- 8 - B 18 OR2 0 3 1 0 |wybed_7seg:51|:186
- 1 - B 14 OR2 s 0 4 0 2 |wybed_7seg:51|~187~1
- 2 - B 18 OR2 s 0 4 0 1 |wybed_7seg:51|~187~2
- 4 - B 18 OR2 s 0 4 0 1 |wybed_7seg:51|~187~3
- 7 - B 18 OR2 0 2 1 0 |wybed_7seg:51|:187
- 1 - B 18 OR2 s 0 4 0 2 |wybed_7seg:51|~188~1
- 5 - B 18 OR2 s 0 4 0 1 |wybed_7seg:51|~188~2
- 6 - B 18 OR2 0 2 1 0 |wybed_7seg:51|:188
- 4 - B 05 DFFE 3 0 1 9 |wycdu16:36|74161:6|f74161:sub|QA (|wycdu16:36|74161:6|f74161:sub|:9)
- 8 - B 05 AND2 1 1 0 3 |wycdu16:36|74161:6|f74161:sub|:80
- 5 - B 05 DFFE 2 1 1 10 |wycdu16:36|74161:6|f74161:sub|QB (|wycdu16:36|74161:6|f74161:sub|:87)
- 2 - B 05 DFFE 2 2 1 9 |wycdu16:36|74161:6|f74161:sub|QC (|wycdu16:36|74161:6|f74161:sub|:99)
- 3 - B 05 DFFE 2 3 1 8 |wycdu16:36|74161:6|f74161:sub|QD (|wycdu16:36|74161:6|f74161:sub|:110)
- 7 - B 17 DFFE 2 3 0 3 |wycdu16:40|74161:6|f74161:sub|QA (|wycdu16:40|74161:6|f74161:sub|:9)
- 6 - B 17 AND2 0 4 0 3 |wycdu16:40|74161:6|f74161:sub|:80
- 4 - B 17 DFFE 2 1 0 4 |wycdu16:40|74161:6|f74161:sub|QB (|wycdu16:40|74161:6|f74161:sub|:87)
- 3 - B 17 DFFE 2 2 0 3 |wycdu16:40|74161:6|f74161:sub|QC (|wycdu16:40|74161:6|f74161:sub|:99)
- 1 - B 17 DFFE 2 3 0 2 |wycdu16:40|74161:6|f74161:sub|QD (|wycdu16:40|74161:6|f74161:sub|:110)
- 7 - B 10 DFFE 3 0 0 4 |wycdu16:41|74161:6|f74161:sub|QA (|wycdu16:41|74161:6|f74161:sub|:9)
- 4 - B 10 AND2 1 2 0 4 |wycdu16:41|74161:6|f74161:sub|:84
- 3 - B 10 DFFE 3 1 0 3 |wycdu16:41|74161:6|f74161:sub|QB (|wycdu16:41|74161:6|f74161:sub|:87)
- 2 - B 17 DFFE 2 1 0 5 |wycdu16:41|74161:6|f74161:sub|QC (|wycdu16:41|74161:6|f74161:sub|:99)
- 8 - B 17 DFFE 2 2 0 4 |wycdu16:41|74161:6|f74161:sub|QD (|wycdu16:41|74161:6|f74161:sub|:110)
- 2 - A 10 DFFE +s 0 0 1 0 |wyscan:50|tt~1~2
- 8 - B 03 DFFE + 0 0 1 4 |wyscan:50|tt~1
- 1 - B 03 OR2 ! 0 3 0 12 |wyscan:50|:57
- 5 - B 17 OR2 0 3 0 12 |wyscan:50|:59
- 5 - B 14 OR2 0 3 0 12 |wyscan:50|:61
- 1 - B 10 OR2 0 3 0 12 |wyscan:50|:63
- 2 - B 12 AND2 2 0 0 8 :21
- 1 - B 12 AND2 2 0 0 8 :24
- 8 - B 06 AND2 2 0 0 8 :30
- 6 - B 06 AND2 2 0 0 8 :46
- 1 - B 05 OR2 ! 0 4 0 2 |74181:2|:43
- 3 - B 09 OR2 ! 0 4 0 2 |74181:2|:44
- 6 - B 13 OR2 ! 0 4 0 3 |74181:2|:45
- 6 - B 05 OR2 ! 0 4 0 2 |74181:2|:46
- 1 - B 09 OR2 ! 0 4 0 2 |74181:2|:47
- 8 - B 13 OR2 ! 0 4 0 2 |74181:2|:48
- 4 - B 23 OR2 0 4 0 2 |74181:2|:51
- 8 - B 12 OR2 0 4 0 2 |74181:2|:52
- 3 - B 23 OR2 1 2 0 1 |74181:2|:74
- 1 - B 01 OR2 s 1 2 0 2 |74181:2|CN4~1 (|74181:2|~78~1)
- 8 - B 09 OR2 s 0 3 0 2 |74181:2|CN4~2 (|74181:2|~78~2)
- 1 - B 20 OR2 s 0 2 0 2 |74181:2|CN4~3 (|74181:2|~78~3)
- 1 - B 23 OR2 ! 0 4 0 2 |74181:2|CN4 (|74181:2|:78)
- 3 - B 01 OR2 s 2 1 0 1 |74181:2|~80~1
- 2 - B 09 OR2 1 3 0 1 |74181:2|:81
- 4 - B 20 OR2 1 3 0 1 |74181:2|:82
- 1 - B 13 OR2 0 4 0 2 |74181:3|:43
- 2 - B 16 OR2 0 4 0 3 |74181:3|:44
- 7 - B 09 OR2 0 4 0 3 |74181:3|:45
- 4 - B 24 OR2 0 4 0 2 |74181:3|:46
- 1 - B 16 OR2 0 4 0 3 |74181:3|:47
- 4 - B 09 OR2 0 4 0 2 |74181:3|:48
- 3 - B 16 OR2 0 4 0 2 |74181:3|:51
- 5 - B 16 OR2 0 4 0 2 |74181:3|:52
- 1 - B 22 OR2 s 0 4 0 2 |74181:3|~74~1
- 3 - B 19 OR2 1 2 0 1 |74181:3|:74
- 5 - B 22 OR2 s 0 3 0 1 |74181:3|~75~1
- 6 - B 19 OR2 0 4 1 0 |74181:3|CN4 (|74181:3|:78)
- 8 - B 24 OR2 s 0 3 0 3 |74181:3|~79~1
- 5 - B 24 OR2 1 3 0 1 |74181:3|:80
- 3 - B 21 OR2 1 3 0 1 |74181:3|:81
- 6 - B 22 OR2 1 3 0 1 |74181:3|:82
- 5 - B 10 OR2 s 2 2 0 1 |74244:1|~1~1~3~2
- 2 - B 10 OR2 1 3 1 0 |74244:1|~1~1~3
- 2 - B 01 OR2 1 2 0 1 |74244:1|~1~2
- 1 - B 06 OR2 s 2 2 0 1 |74244:1|~6~1~3~2
- 2 - B 06 OR2 s 1 2 0 1 |74244:1|~6~1~3~3
- 5 - B 06 OR2 1 2 1 0 |74244:1|~6~1~3
- 2 - B 20 OR2 s 2 2 0 1 |74244:1|~10~1~3~2
- 3 - B 20 OR2 s 1 2 0 1 |74244:1|~10~1~3~3
- 6 - B 20 OR2 1 2 1 0 |74244:1|~10~1~3
- 2 - B 23 OR2 s 2 2 0 1 |74244:1|~11~1~3~2
- 8 - B 23 OR2 1 3 1 0 |74244:1|~11~1~3
- 5 - B 23 OR2 1 3 0 1 |74244:1|~11~2
- 2 - B 19 OR2 s 2 2 0 1 |74244:1|~26~1~3~2
- 4 - B 19 OR2 1 3 1 0 |74244:1|~26~1~3
- 5 - B 19 OR2 1 3 0 1 |74244:1|~26~2
- 3 - B 22 OR2 s 2 2 0 1 |74244:1|~27~1~3~2
- 2 - B 22 OR2 1 3 1 0 |74244:1|~27~1~3
- 1 - B 19 OR2 4 0 0 0 |74244:1|~31~1~2
- 1 - B 21 OR2 s 2 2 0 1 |74244:1|~31~1~3~2
- 2 - B 21 OR2 s 1 2 0 1 |74244:1|~31~1~3~3
- 5 - B 21 OR2 1 2 1 0 |74244:1|~31~1~3
- 2 - B 24 OR2 s 2 2 0 1 |74244:1|~36~1~3~2
- 3 - B 24 OR2 s 1 2 0 1 |74244:1|~36~1~3~3
- 1 - B 24 OR2 1 2 1 0 |74244:1|~36~1~3
- 7 - B 16 DFFE 0 2 0 2 |74273:15|Q8 (|74273:15|:12)
- 5 - B 09 DFFE 0 2 0 2 |74273:15|Q7 (|74273:15|:13)
- 4 - B 16 DFFE 0 2 0 2 |74273:15|Q6 (|74273:15|:14)
- 7 - B 13 DFFE 0 2 0 2 |74273:15|Q5 (|74273:15|:15)
- 6 - B 12 DFFE 0 2 0 2 |74273:15|Q4 (|74273:15|:16)
- 3 - B 13 DFFE 0 2 0 2 |74273:15|Q3 (|74273:15|:17)
- 4 - B 12 DFFE 0 2 0 2 |74273:15|Q2 (|74273:15|:18)
- 2 - B 13 DFFE 0 2 0 2 |74273:15|Q1 (|74273:15|:19)
- 8 - B 16 DFFE 0 2 0 2 |74273:16|Q8 (|74273:16|:12)
- 6 - B 09 DFFE 0 2 0 2 |74273:16|Q7 (|74273:16|:13)
- 6 - B 16 DFFE 0 2 0 2 |74273:16|Q6 (|74273:16|:14)
- 5 - B 13 DFFE 0 2 0 2 |74273:16|Q5 (|74273:16|:15)
- 7 - B 12 DFFE 0 2 0 2 |74273:16|Q4 (|74273:16|:16)
- 4 - B 13 DFFE 0 2 0 2 |74273:16|Q3 (|74273:16|:17)
- 3 - B 12 DFFE 0 2 0 2 |74273:16|Q2 (|74273:16|:18)
- 7 - B 05 DFFE 0 2 0 2 |74273:16|Q1 (|74273:16|:19)
- 6 - B 10 DFFE 0 2 0 1 |74374:17|:13
- 4 - B 06 DFFE 0 2 0 1 |74374:17|:14
- 7 - B 20 DFFE 0 2 0 1 |74374:17|:15
- 7 - B 23 DFFE 0 2 0 1 |74374:17|:16
- 7 - B 24 DFFE 0 2 0 1 |74374:17|:17
- 6 - B 21 DFFE 0 2 0 1 |74374:17|:18
- 8 - B 22 DFFE 0 2 0 1 |74374:17|:19
- 8 - B 19 DFFE 0 2 0 1 |74374:17|:20
- 4 - B 22 OR2 1 1 0 1 |74374:17|~46~1
- 1 - B 04 DFFE 0 2 0 1 |74374:18|:13
- 3 - B 06 DFFE 0 2 0 1 |74374:18|:14
- 5 - B 20 DFFE 0 2 0 1 |74374:18|:15
- 6 - B 23 DFFE 0 2 0 1 |74374:18|:16
- 6 - B 24 DFFE 0 2 0 1 |74374:18|:17
- 4 - B 21 DFFE 0 2 0 1 |74374:18|:18
- 7 - B 22 DFFE 0 2 0 1 |74374:18|:19
- 7 - B 19 DFFE 0 2 0 1 |74374:18|:20
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\program\edamaxplus\exm3\wyyunsuanqi.rpt
wyyunsuanqi
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/ 96( 1%) 1/ 48( 2%) 0/ 48( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
B: 47/ 96( 48%) 13/ 48( 27%) 25/ 48( 52%) 1/16( 6%) 3/16( 18%) 0/16( 0%)
C: 4/ 96( 4%) 0/ 48( 0%) 0/ 48( 0%) 2/16( 12%) 2/16( 12%) 0/16( 0%)
D: 1/ 96( 1%) 0/ 48( 0%) 0/ 48( 0%) 1/16( 6%) 0/16( 0%) 0/16( 0%)
E: 4/ 96( 4%) 0/ 48( 0%) 0/ 48( 0%) 4/16( 25%) 0/16( 0%) 0/16( 0%)
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -