📄 f51mble3.a51
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;************************************************************************
;* SST FlashFlex51 Boot-Strap Loader(BSL) *
;* (F51MBLE3.A51 - Version 1.1E) *
;* (for SST89C58 MCU - Device Code: E2h) *
;* (MCU with 11.0592 MHz Ext. Crystal/38.4 Kbps baud rate) *
;* *
;* NOTE: *
;* 1. It's no longer need to check the port pin P1.0 to decide whether *
;* to execute BSL IAP cmd or to run user code during BSL routine. *
;* 2. In BSL, the firmware(fw) sets the Watchdog Timer(WDT) for a time *
;* period of 50 ms, sends a query cmd(F7h) to host PC and waits for *
;* hand-shaking cmd(05h & 55h) from PC before WDT timeout. Upon *
;* detecting the hand-shaking cmd, the fw sends its ID - three *
;* consecutive bytes: device code, fw version and fw revision - to *
;* host PC, and then waits for Pseudo IAP cmd from PC with new time- *
;* out of 2 seconds. *
;* 3. The fw will execute user code at 0000h after WDT timeout. *
;* 4. From the host PC, the user can issue a run-usercode cmd(62h & 62h)*
;* to stop BSL mode and to executes user code instead. *
;* 5. The fw supports a 38.4 Kbps baud for serial port with an external *
;* OSC of 12 MHz. The previous version only supports a 9.6 Kbps baud.*
;* 6. Unlike previous version, this fw uses a polling algorithm rather *
;* than using interrupt-driven rs232_isr to access serial port. For *
;* users plan to overwrite the fw in block 1 of flash, this feature *
;* can facilitate the incorporation of user code into BSL routines. *
;* 7. The pseudo IAP cmd of SECURITY-LOCK(SFCM_SB) and BLOCK-ERASE *
;* (SFCM_BE) has been moved to External Memory Mode(EA# = 1)- please *
;* refers to F51EBLE.A51/F51EBLF.A51 of fw v1.1E. *
;* 8. This fw is referred as the "Internal Memory Mode(EA# = 1)" by the *
;* host PC and is loaded into block 1 of flash. To execute the BSL *
;* after reset, the user needs to remap 1KB/2KB/4KB of flash memory *
;* from External Memory Mode or External Host Mode(RST = 1 and PSEN# *
;* = 0) which often used by a standalone universal programmer. *
;* 9. FW withholds the following resources: *
;* Registers R0-R6 in register bank 0; Internal RAM 08h-0Fh; *
;* Watchdog Timer (WDT); Registers: A, B, DPTR, SFCF registers. *
;*10. Companion SST89C54/C58 MCU datasheet/specifications should be *
;* reviewed in conjunction with this application note for a complete *
;* understand of the device. *
;* *
;************************************************************************
;* Developer: Frank Cirimele *
;* SST Embedded Controller Application Engineering *
;* *
;* Contact: Silicon Storage Technology Inc. *
;* 1171 Sonora Court *
;* Sunnyvale, CA 94086 *
;* phone: (408)522-7352 *
;* fax: (408)749-9658 *
;* email: cirimele@ssti.com *
;* *
;* Original Code Release Date: 6-08-2001 *
;* *
;************************************************************************
;************************************************************************
;* *
;* 8052 Family Special Function Registers(SFRs) Memory Locations *
;* *
;************************************************************************
T2CON DATA 0C8H ; Timer/Counter 2 Control
RCAP2L DATA 0CAH ; Auto-Reload/Capture 2 Low Byte
RCAP2H DATA 0CBH ; Auto-Reload/Capture 2 High Byte
TL2 DATA 0CCH ; Timer/Counter 2 Low Byte
TH2 DATA 0CDH ; Timer/Counter 2 High Byte
;************************************************************************
;* *
;* FlashFlex51 MCU SST89C54/58 SFR Memory locations *
;* *
;************************************************************************
SFCF DATA 0B1H ; SuperFlash Configuration
SFCM DATA 0B2H ; SuperFlash Command
SFAL DATA 0B3H ; SuperFlash Address Low
SFAH DATA 0B4H ; SuperFlash Address High
SFDT DATA 0B5H ; SuperFlash Data
SFST DATA 0B6H ; SuperFlash Status
WDTC DATA 0C0H ; Watchdog Timer Control
WDTD DATA 86H ; Watchdog Timer Data/Reload
;************************************************************************
;* *
;* FlashFlex51 MCU SST89C54/58 IAP Commands *
;* *
;************************************************************************
SFCM_SE EQU 0BH ; Sector erase cmd
SFCM_PB EQU 0EH ; Program byte cmd
SFCM_BP EQU 06H ; Burst program cmd
SFCM_VB EQU 0CH ; Verify byte cmd
;************************************************************************
;* *
;* Variables Definition *
;* *
;************************************************************************
CMD EQU R2 ; PC command
PCDATA EQU R3 ; PC data
ADRHI EQU R4 ; start address - high byte
ADRLO EQU R5 ; start address - low byte
COUNT EQU R6 ; byte count or size
STR1 DATA 08h ; internal RAM 08h - 0Bh is used to store STRG
STR2 DATA 09h
STR3 DATA 0Ah
STR4 DATA 0Bh
;************************************************************************
;* *
;* Constants Definition *
;* *
;************************************************************************
SST89C54_ID EQU 0E4h ; Device code of SST89C54 MCU
SST89C58_ID EQU 0E2h ; Device code of SST89C58 MCU
FW_Ver EQU 11h ; BSL firmware version 1.1
FW_Rev EQU 'E' ; BSL firmware revision E, ie. BSL v1.1E
;************************************************************************
;* *
;* RESET AND INTERRUPT VECTORS (SECTOR 0 in BLOCK 1 of FLASH) *
;* *
;************************************************************************
org 0F000h ; reset vector after remapped 1K/2K/4K
ljmp start ; jump to start code
org 0F003h ; external interrupt 0 vector
org 0F00Bh ; timer 0 overflow vector
org 0F013h ; external interrupt 1 vector
org 0F01Bh ; timer 1 overflow vector
org 0F023h ; serial I/O interrupt vector
org 0F02Bh ; timer 2 overflow vector
;************************************************************************
;* *
;* BOOT CODE OR USER CODE? *
;* * *
;************************************************************************
;* During BSL start routine, the fw check the WDTC.2 (Watchdog timer *
;* reset flag) and jump to BSL poweron routine if WDTC.2 = 0 or compare *
;* STR1 thru STR4 with string "POWR" or "USER" if WDTC.2 = 1 (timeout *
;* detected). *
;* *
;* After WDT timeout, the firmware takes the following steps: *
;* 1. Clear WDT reset flag if WDT expires in BSL1.1E, rather than in *
;* user code. *
;* 2. Jump to resetval routine to restore SFRs reset values. *
;* 3. Jump to 0000h in block 0 of flash to execute user code. *
;* * *
;************************************************************************
org 0F040h-2
sjmp $
org 0F040h
start: mov a, SFCF ; jump to chkwdtc if remap is set
anl a, #00000011b
jnz chkwdtc
mov STR1, #"R" ; if remap is not set, then set flag of "RMAP"
mov STR2, #"M"
mov STR3, #"A"
mov STR4, #"P"
mov WDTD, #-2 ; wait 10ms(typ.) to reset MCU
mov WDTC, #0fh ; in order to detect real remapping value
sjmp $ ; software trap remapping
chkwdtc:jnb WDTC.2, poweron ; jump to init after Power-On-Reset
mov a, STR1
cjne a, #'P', others
mov a, STR2
cjne a, #'O', others
mov a, STR3
cjne a, #'W', others
mov a, STR4
cjne a, #'R', others
orl WDTC, #00000100b ; clear the reset flag ( WDTS, ie WDTC.2 )
ljmp resetval ; long jump to resetval if flag is "POWR"
others: mov a, STR1
cjne a, #'U', rmap
mov a, STR2
cjne a, #'S', rmap
mov a, STR3
cjne a, #'E', rmap
mov a, STR4
cjne a, #'R', rmap
; jump to resetval if flag="USER" and WDTC.2=1
ljmp resetval ; but don't clear WDT reset flag (WDTS) !!
rmap: mov a, STR1
cjne a, #'R', user
mov a, STR2
cjne a, #'M', user
mov a, STR3
cjne a, #'A', user
mov a, STR4
cjne a, #'P', user
orl WDTC, #00000100b ; clear reset flag
sjmp poweron
user: mov STR1, #'U' ; set flag of "USER"
mov STR2, #'S'
mov STR3, #'E'
mov STR4, #'R'
sjmp init
;************************************************************************
;* *
;* BSL INIT ROUTINE: INITIALIZATION CODE *
;* *
;************************************************************************
;* 1. Initialize SFRs, set up serial connection and start WDT. *
;* 2. MCU sends Query cmd(F7h) to host PC and waits for hand-shaking *
;* cmd(05h & 55h) from PC and then reports the status byte to PC. *
;* 3. MCU sends cmd F7h to PC and waits for cmd 60h from PC and report *
;* the chip ID and fw ID to PC. *
;* 4. The fw stays in a loop routine: MCU sends cmd F7h to PC and waits *
;* for pseudo IAP cmd from PC. *
;* 5. To stop the loop routine, either apply a reset or the PC sends a *
;* Run-usercode cmd(62h) to MCU. *
;* *
;************************************************************************
poweron: ; set flag of "POWR"
mov STR1, #'P'
mov STR2, #'O'
mov STR3, #'W'
mov STR4, #'R'
init: clr a ; clear Accumulator
mov PSW, a ; clear Program Status Word
mov IE, a ; clear Interrupt Enable
mov SP, #0Bh ; 0Ch thru 0Fh used as Stack!
anl SFCF, #00111111b ; VIS=0, IAPEN=0
mov SFDT, #0 ; any value other than 55h
mov SFAH, #0abh ; point to off-chip memory
mov SFAL, #0cdh
mov RCAP2H, #high(-9) ; 11.0592 MHz OSC, for 38.4K bps
mov RCAP2L, #low(-9) ; 11.0592 MHz OSC, for 38.4K bps
; mov RCAP2H, #high(-10) ; 12 MHz OSC, for 38.4K bps
; mov RCAP2L, #low(-10) ; 12 MHz OSC, for 38.4K bps
mov T2CON, #00110100b ; Timer2 as baudrate generator for RCLK+TCLK
mov SCON, #01010010b ; mode1, 8bit UART, no parity, REN=1, TI=1
mov WDTD, #-5 ; count up to 5 x 7.7ms=38ms(min.), 50ms(typ.)
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