ft1505a4_cmo2d4_combix_v01(for cmo2.4).c

FT1505A4配CMO2.4"玻璃的初始化代码

	RESET=0;
	delay_ms(50);
	RESET=1;
	delay_ms(10);  //waiting for releasing reset

	delay_ms(50);
	//interface synchronous
	wr_reg(0xff);//
	wr_reg(0x00);
	wr_reg(0x00);
	wr_reg(0x00);
	wr_reg(0x00);
	//synchronous end
	
	wr_reg(0xB0);
	wr_cmd(0x00,0x01);    //
		
	wr_reg(0x00);
	wr_cmd(0x00,0x01);	//start oscilation
	delay_ms(50);
	
	wr_reg(0x07);
	wr_cmd(0x00,0x00);	//DTE=0, GON=0,D=00
	delay_ms(50);
	
	wr_reg(0x12);
	wr_cmd(0x00,0x00);	//PON=0,VON=0
	delay_ms(50);

	wr_reg(0x70);
	wr_cmd(0x27,0x00);	//GS=0, NL=11011, SCN=00000
	
	wr_reg(0x08);
	wr_cmd(0x04,0x05);	//BP=0101, FP=0100
	
	//gamma setting  
	/////////////////////////////////////////////////////////////////

	wr_reg(0x30);
	wr_cmd(0x00,0x00);  //pkp1 pkp0
	
	wr_reg(0x31);     
	wr_cmd(0x01,0x05);  //pkp3 pkp2
	                  
	wr_reg(0x32);     
	wr_cmd(0x00,0x04);  //pkp5 pkp4
	                  
	wr_reg(0x33);     
	wr_cmd(0x00,0x06);  //prp1 prp0
	                  
	wr_reg(0x34);     
	wr_cmd(0x01,0x05);  //pkn1 pkn0
	                  
	wr_reg(0x35);     
	wr_cmd(0x00,0x01);  //pkn3 pkn2
	                  
	wr_reg(0x36);     
	wr_cmd(0x07,0x07);  //pkn5 pkn4
	                          
	wr_reg(0x37);            
	wr_cmd(0x07,0x04);  //prn1 prn0
	                          
	wr_reg(0x38);             
	wr_cmd(0x03,0x00);  //vrp1 vrp0

        wr_reg(0x39);
	wr_cmd(0x08,0x00);  //vrn1 vrn0                      

	///////////////////////////////////////////////////////////////////
	
	//Power setting
	wr_reg(0x15);
	wr_cmd(0x00,0x01);	//SAPSEL=1
	
	wr_reg(0x10);
	wr_cmd(0x66,0xb0);	//

	wr_reg(0x11);           //      
	wr_cmd(0x02,0x57);   	
	delay_ms(20);
	
	wr_reg(0x12);
	wr_cmd(0x01,0x08);	//
	delay_ms(30);
	
	wr_reg(0x12);
	wr_cmd(0x01,0x18);	//
	delay_ms(30);

	wr_reg(0x13);
	wr_cmd(0xa2,0x07);      //

	delay_ms(30);
	
	//display setting
	wr_reg(0x01);
	wr_cmd(0x01,0x00);	//
	
	wr_reg(0x02);
	wr_cmd(0x07,0x00);	//
	
	wr_reg(0x03);           //565
	wr_cmd(0x40,0x30);	//BGR=1, I/D=11, AM=0, DFM=10     note: put the highest bit to lowest bit.
	
	
	wr_reg(0x71);
	wr_cmd(0x00,0x01);	//VLE=00, REV=1

	
	wr_reg(0x90);           //frame freq set
	wr_cmd(0x01,0x08);	//DIVI=02, RTNI=1001

	
	wr_reg(0x91);
	wr_cmd(0x00,0x00);	//NOI=000
	
	wr_reg(0x92);           //EQ time set
	wr_cmd(0x00,0x00);	//STDI=000 EQI=0
	
	wr_reg(0x09);
	wr_cmd(0x00,0x00);
	
	wr_reg(0x80);
	wr_cmd(0x00,0x00);

	wr_reg(0x81);
	wr_cmd(0x00,0x00);	//PTSA=000
	
	wr_reg(0x82);
	wr_cmd(0x01,0x3F);

	wr_reg(0x83);
	wr_cmd(0x00,0x00);	//PTSA=000
	
	wr_reg(0x84);
	wr_cmd(0x00,0x00);
	
	wr_reg(0x85);
	wr_cmd(0x01,0x3F);
	
	wr_reg(0x50);
        wr_cmd(0x00,0x00);
    	
        wr_reg(0x51);
        wr_cmd(0x00,0xEF);
        
        wr_reg(0x52);
        wr_cmd(0x00,0x00);
        
        wr_reg(0x53);
        wr_cmd(0x01,0x3F);

//  disp_on

	wr_reg(0x10);
        wr_cmd(0x76,0xb0);
	delay_ms(20);
	
	wr_reg(0x07);
	wr_cmd(0x00,0x01);	//GON=0, DTE=0, D=01
	delay_ms(20);
	
	wr_reg(0x07);
	wr_cmd(0x00,0x21);	//GON=1, DTE=1, D=01

	wr_reg(0x12);
	wr_cmd(0x11,0x18);	//VON=1,VCMR=1, PON=1,VRH=1000
	delay_ms(20);
	
	wr_reg(0x07);
	wr_cmd(0x02,0x33);	//BASEE=1, GON=1, DTE=1, D=11