rtl8139.h

Minix3.11的源码。[MINIX 3是一个为高可靠性应用而设计的自由且简洁的类UNIX系统。]

/*
ibm/rtl8139.h

Created:	Aug 2003 by Philip Homburg <[e-mail]>
*/

#define	RL_IDR		0x00	/* Ethernet address
				 * Note: RL_9346CR_EEM_CONFIG mode is
				 * required the change the ethernet
				 * address.
				 * Note: 4-byte write access only.
				 */
#define		RL_N_TX		4	/* Number of transmit buffers */
#define	RL_TSD0	0x010	/* Transmit Status of Descriptor 0 */
#define		RL_TSD_CRS	0x80000000 /* Carrier Sense Lost */
#define		RL_TSD_TABT	0x40000000 /* Transmit Abort */
#define		RL_TSD_OWC	0x20000000 /* Out of Window Collision */
#define		RL_TSD_CDH	0x10000000 /* CD Heart Beat */
#define		RL_TSD_NCC_M	0x0F000000 /* Number of Collision Count */
#define		RL_TSD_RES	0x00C00000 /* Reserved */
#define		RL_TSD_ERTXTH_M	0x003F0000 /* Early Tx Threshold */
#define			RL_TSD_ERTXTH_S		16		/* shift */
#define			RL_TSD_ERTXTH_8		0x00000000	/* 8 bytes */
#define		RL_TSD_TOK	0x00008000 /* Transmit OK */
#define		RL_TSD_TUN	0x00004000 /* Transmit FIFO Underrun */
#define		RL_TSD_OWN	0x00002000 /* Controller (does not) Own Buf. */
#define		RL_TSD_SIZE	0x00001FFF /* Descriptor Size */
#define RL_TSAD0	0x20	/* Transmit Start Address of Descriptor 0 */
#define RL_RBSTART	0x30	/* Receive Buffer Start Address */
#define	RL_CR		0x37	/* Command Register */
#define		RL_CR_RES0	0xE0	/* Reserved */
#define		RL_CR_RST	0x10	/* Reset */
#define		RL_CR_RE	0x08	/* Receiver Enable */
#define		RL_CR_TE	0x04	/* Transmitter Enable *
					 * Note: start with transmit buffer
					 * 0 after RL_CR_TE has been reset.
					 */
#define		RL_CR_RES1	0x02	/* Reserved */
#define		RL_CR_BUFE	0x01	/* Receive Buffer Empty */
#define	RL_CAPR		0x38	/* Current Address of Packet Read */
#define		RL_CAPR_DATA_OFF	0x10	/* Packet Starts at Offset */
#define	RL_CBR		0x3A	/* Current Buffer Address */
#define	RL_IMR		0x3C	/* Interrupt Mask Register */
#define		RL_IMR_SERR	0x8000	/* System Error */
#define		RL_IMR_TIMEOUT	0x4000	/* Time Out */
#define		RL_IMR_LENCHG	0x2000	/* Cable Length Change */
#define		RL_IMR_RES	0x1F80	/* Reserved */
#define		RL_IMR_FOVW	0x0040	/* Rx FIFO Overflow */
#define		RL_IMR_PUN	0x0020	/* Packet Underrun / Link Change */
#define		RL_IMR_RXOVW	0x0010	/* Rx Buffer Overflow */
#define		RL_IMR_TER	0x0008	/* Transmit Error */
#define		RL_IMR_TOK	0x0004	/* Transmit OK */
#define		RL_IMR_RER	0x0002	/* Receive Error */
#define		RL_IMR_ROK	0x0001	/* Receive OK */
#define	RL_ISR		0x3E	/* Interrupt Status Register */
#define		RL_ISR_SERR	0x8000	/* System Error */
#define		RL_ISR_TIMEOUT	0x4000	/* Time Out */
#define		RL_ISR_LENCHG	0x2000	/* Cable Length Change */
#define		RL_ISR_RES	0x1F80	/* Reserved */
#define		RL_ISR_FOVW	0x0040	/* Rx FIFO Overflow */
#define		RL_ISR_PUN	0x0020	/* Packet Underrun / Link Change */
#define		RL_ISR_RXOVW	0x0010	/* Rx Buffer Overflow */
#define		RL_ISR_TER	0x0008	/* Transmit Error */
#define		RL_ISR_TOK	0x0004	/* Transmit OK */
#define		RL_ISR_RER	0x0002	/* Receive Error */
#define		RL_ISR_ROK	0x0001	/* Receive OK */
#define	RL_TCR		0x40	/* Transmit Configuration Register
				 * Note: RL_CR_TE has to be set to
				 * set/change RL_TCR.
				 */
#define		RL_TCR_RES0	0x80000000 /* Reserved */
#define		RL_TCR_HWVER_AM 0x7C000000 /* Hardware Version ID A */
#define		RL_TCR_IFG_M	0x03000000 /* Interframe Gap Time */
#define			RL_TCR_IFG_STD		0x03000000 /* IEEE 802.3 std */
#if 0
#undef RL_TCR_IFG_STD
#define			RL_TCR_IFG_STD		0x00000000 
#endif
#define		RL_TCR_HWVER_BM	0x00C00000 /* Hardware Version ID B */
#define			RL_TCR_HWVER_RTL8139	0x60000000 /* RTL8139 */
#define			RL_TCR_HWVER_RTL8139A	0x70000000 /* RTL8139A */
#define			RL_TCR_HWVER_RTL8139AG	0x74000000 /* RTL8139A-G */
#define			RL_TCR_HWVER_RTL8139B	0x78000000 /* RTL8139B */
#define			RL_TCR_HWVER_RTL8130	0x78000000 /* RTL8130 (dup) */
#define			RL_TCR_HWVER_RTL8139C	0x74000000 /* RTL8139C (dup) */
#define			RL_TCR_HWVER_RTL8100	0x78800000 /* RTL8100 */
#define			RL_TCR_HWVER_RTL8100B	0x74400000 /* RTL8100B /
								RTL8139D */
#define			RL_TCR_HWVER_RTL8139CP	0x74800000 /* RTL8139C+ */
#define			RL_TCR_HWVER_RTL8101	0x74C00000 /* RTL8101 */
#define		RL_TCR_RES1	0x00380000 /* Reserved */
#define		RL_TCR_LBK_M	0x00060000 /* Loopback Test */
#define			RL_TCR_LBK_NORMAL	0x00000000 /* Normal */
#define			RL_TCR_LBK_LOOKBOCK	0x00060000 /* Loopback Mode */
#define		RL_TCR_CRC	0x00010000 /* (Do not) Append CRC */
#define		RL_TCR_RES2	0x0000F800 /* Reserved */
#define		RL_TCR_MXDMA_M	0x00000700 /* Max DMA Burst Size Tx */
#define			RL_TCR_MXDMA_16		0x00000000 /* 16 bytes */
#define			RL_TCR_MXDMA_32		0x00000100 /* 32 bytes */
#define			RL_TCR_MXDMA_64		0x00000200 /* 64 bytes */
#define			RL_TCR_MXDMA_128	0x00000300 /* 128 bytes */
#define			RL_TCR_MXDMA_128	0x00000300 /* 128 bytes */
#define			RL_TCR_MXDMA_256	0x00000400 /* 256 bytes */
#define			RL_TCR_MXDMA_512	0x00000500 /* 512 bytes */
#define			RL_TCR_MXDMA_1024	0x00000600 /* 1024 bytes */
#define			RL_TCR_MXDMA_2048	0x00000700 /* 2048 bytes */
#define		RL_TCR_TXRR_M	0x000000F0 /* Tx Retry Count */
#define		RL_TCR_RES3	0x0000000E /* Reserved */
#define		RL_TCR_CLRABT	0x00000001 /* Clear Abort */
#define RL_RCR		0x44	/* Receive Configuration Register
				 * Note: RL_CR_RE has to be set to
				 * set/change RL_RCR.
				 */
#define		RL_RCR_RES0	0xF0000000 /& Reserved */
#define		RL_RCR_ERTH_M	0x0F000000 /* Early Rx Threshold */
#define			RL_RCR_ERTH_0		0x00000000 /* No threshold */
#define			RL_RCR_ERTH_1		0x01000000 /* 1/16 */
#define			RL_RCR_ERTH_2		0x02000000 /* 2/16 */
#define			RL_RCR_ERTH_3		0x03000000 /* 3/16 */
#define			RL_RCR_ERTH_4		0x04000000 /* 4/16 */
#define			RL_RCR_ERTH_5		0x05000000 /* 5/16 */
#define			RL_RCR_ERTH_6		0x06000000 /* 6/16 */
#define			RL_RCR_ERTH_7		0x07000000 /* 7/16 */
#define			RL_RCR_ERTH_8		0x08000000 /* 8/16 */
#define			RL_RCR_ERTH_9		0x09000000 /* 9/16 */
#define			RL_RCR_ERTH_10		0x0A000000 /* 10/16 */
#define			RL_RCR_ERTH_11		0x0B000000 /* 11/16 */
#define			RL_RCR_ERTH_12		0x0C000000 /* 12/16 */
#define			RL_RCR_ERTH_13		0x0D000000 /* 13/16 */
#define			RL_RCR_ERTH_14		0x0E000000 /* 14/16 */
#define			RL_RCR_ERTH_15		0x0F000000 /* 15/16 */
#define		RL_RCR_RES1	0x00FC0000 /* Reserved */
#define		RL_RCR_MULERINT	0x00020000 /* Multiple Early Int Select */
#define		RL_RCR_RER8	0x00010000 /* Receive small error packet */
#define		RL_RCR_RXFTH_M	0x0000E000 /* Rx FIFO Threshold */
#define			RL_RCR_RXFTH_16		0x00000000 /* 16 bytes */
#define			RL_RCR_RXFTH_32		0x00002000 /* 32 bytes */
#define			RL_RCR_RXFTH_64		0x00004000 /* 64 bytes */
#define			RL_RCR_RXFTH_128	0x00006000 /* 128 bytes */
#define			RL_RCR_RXFTH_256	0x00008000 /* 256 bytes */
#define			RL_RCR_RXFTH_512	0x0000A000 /* 512 bytes */
#define			RL_RCR_RXFTH_1024	0x0000C000 /* 1024 bytes */
#define			RL_RCR_RXFTH_UNLIM	0x0000E000 /* unlimited */
#define		RL_RCR_RBLEM_M	0x00001800 /* Rx Buffer Length */
#define			RL_RCR_RBLEN_8K		0x00000000 /* 8KB + 16 bytes */
#define			RL_RCR_RBLEN_8K_SIZE	(8*1024)
#define			RL_RCR_RBLEN_16K	0x00000800 /* 16KB + 16 bytes */
#define			RL_RCR_RBLEN_16K_SIZE	(16*1024)
#define			RL_RCR_RBLEN_32K	0x00001000 /* 32KB + 16 bytes */
#define			RL_RCR_RBLEN_32K_SIZE	(32*1024)
#define			RL_RCR_RBLEN_64K	0x00001800 /* 64KB + 16 bytes */
#define			RL_RCR_RBLEN_64K_SIZE	(64*1024)
			/* Note: the documentation for the RTL8139C(L) or
			 * for the RTL8139D(L) claims that the buffer should
			 * be 16 bytes larger. Multiples of 8KB are the 
			 * correct values.
			 */
#define		RL_RCR_MXDMA_M	0x00000700 /* Rx DMA burst size */
#define			RL_RCR_MXDMA_16		0x00000000 /* 16 bytes */
#define			RL_RCR_MXDMA_32		0x00000100 /* 32 bytes */
#define			RL_RCR_MXDMA_64		0x00000200 /* 64 bytes */
#define			RL_RCR_MXDMA_128	0x00000300 /* 128 bytes */
#define			RL_RCR_MXDMA_256	0x00000400 /* 256 bytes */
#define			RL_RCR_MXDMA_512	0x00000500 /* 512 bytes */
#define			RL_RCR_MXDMA_1024	0x00000600 /* 1024 bytes */
#define			RL_RCR_MXDMA_UNLIM	0x00000700 /* unlimited */
#define		RL_RCR_WRAP	0x00000080 /* (Do not) Wrap on receive */
#define		RL_RCR_RES2	0x00000040 /* EEPROM type? */
#define		RL_RCR_AER	0x00000020 /* Accept Error Packets */
#define		RL_RCR_AR	0x00000010 /* Accept Runt Packets */
#define		RL_RCR_AB	0x00000008 /* Accept Broadcast Packets */
#define		RL_RCR_AM	0x00000004 /* Accept Multicast Packets */
#define		RL_RCR_APM	0x00000002 /* Accept Physical Match Packets */
#define		RL_RCR_AAP	0x00000001 /* Accept All Packets */
#define	RL_MPC		0x4c	/* Missed Packet Counter */
#define	RL_9346CR	0x50	/* 93C46 Command Register */
#define		RL_9346CR_EEM_M	0xC0	/* Operating Mode */
#define			RL_9346CR_EEM_NORMAL	0x00 /* Normal Mode */
#define			RL_9346CR_EEM_AUTOLOAD	0x40 /* Load from 93C46 */
#define			RL_9346CR_EEM_PROG	0x80 /* 93C46 Programming */
#define			RL_9346CR_EEM_CONFIG	0xC0 /* Config Write Enable */
#define		RL_9346CR_RES	0x30	/* Reserved */
#define		RL_9346CR_EECS	0x08	/* EECS Pin */
#define		RL_9346CR_EESK	0x04	/* EESK Pin */
#define		RL_9346CR_EEDI	0x02	/* EEDI Pin */
#define		RL_9346CR_EEDO	0x01	/* EEDO Pin */
#define RL_CONFIG0	0x51	/* Configuration Register 0 */
#define RL_CONFIG1	0x52	/* Configuration Register 1 */
#define RL_MSR		0x58	/* Media Status Register */
#define		RL_MSR_TXFCE	0x80	/* Tx Flow Control Enable */
#define		RL_MSR_RXFCE	0x40	/* Rx Flow Control Enable */
#define		RL_MSR_RES	0x20	/* Reserved */
#define		RL_MSR_AUXSTAT	0x10	/* Aux. Power Present */
#define		RL_MSR_SPEED_10	0x08	/* In 10 Mbps mode */
#define		RL_MSR_LINKB	0x04	/* link Failed */
#define		RL_MSR_TXPF	0x02	/* Sent Pause Packet */
#define		RL_MSR_RXPF	0x01	/* Received Pause Packet */
#define RL_CONFIG3	0x59	/* Configuration Register 3 */
#define RL_CONFIG4	0x5A	/* Configuration Register 4 */
/*			0x5B */	/* Reserved */
#define RL_REVID	0x5E	/* PCI Revision ID */
/*			0x5F */	/* Reserved */
#define RL_TSAD		0x60	/* Transmit Status of All Descriptors */
#define		RL_TSAD_TOK3	0x8000	/* TOK bit of Descriptor 3 */
#define		RL_TSAD_TOK2	0x4000	/* TOK bit of Descriptor 2 */
#define		RL_TSAD_TOK1	0x2000	/* TOK bit of Descriptor 1 */
#define		RL_TSAD_TOK0	0x1000	/* TOK bit of Descriptor 0 */
#define		RL_TSAD_TUN3	0x0800	/* TUN bit of Descriptor 3 */
#define		RL_TSAD_TUN2	0x0400	/* TUN bit of Descriptor 2 */
#define		RL_TSAD_TUN1	0x0200	/* TUN bit of Descriptor 1 */
#define		RL_TSAD_TUN0	0x0100	/* TUN bit of Descriptor 0 */
#define		RL_TSAD_TABT3	0x0080	/* TABT bit of Descriptor 3 */
#define		RL_TSAD_TABT2	0x0040	/* TABT bit of Descriptor 2 */
#define		RL_TSAD_TABT1	0x0020	/* TABT bit of Descriptor 1 */
#define		RL_TSAD_TABT0	0x0010	/* TABT bit of Descriptor 0 */