📄 rm9200.s
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;// <h> Clock Generator Phase Locked Loop A Register (CKGR_PLLAR)
;// <i> PLL A Freq = (Main CLOCK Freq / DIVA) * (MULA + 1)
;// <o4.0..7> DIVA: PLL Divider A <0-255>
;// <i> 0 - Divider output is 0
;// <i> 1 - Divider is bypassed
;// <i> 2 .. 255 - Divider output is the Main Clock divided by DIVA
;// <o4.8..13> PLLACOUNT: PLL A Counter <0-63>
;// <i> Number of Slow Clocks before the LOCKA bit is set in
;// <i> PMC_SR after CKGR_PLLAR is written
;// <o4.14..15> OUTA: PLL A Clock Frequency Range
;// <0=> 80 .. 160MHz <1=> Reserved
;// <2=> 150 .. 240MHz <3=> Reserved
;// <o4.16..26> MULA: PLL A Multiplier <0-2047>
;// <i> 0 - The PLL A is deactivated
;// <i> 1 .. 2047 - The PLL A Clock frequency is the PLL a input
;// <i> frequency multiplied by MULA + 1
;// </h>
;//
;// <h> Clock Generator Phase Locked Loop B Register (CKGR_PLLBR)
;// <i> PLL B Freq = (Main CLOCK Freq / DIVB) * (MULB + 1)
;// <o5.0..7> DIVB: PLL Divider B <0-255>
;// <i> 0 - Divider output is 0
;// <i> 1 - Divider is bypassed
;// <i> 2 .. 255 - Divider output is the Main Clock divided by DIVB
;// <o5.8..13> PLLBCOUNT: PLL B Counter <0-63>
;// <i> Number of Slow Clocks before the LOCKB bit is set in
;// <i> PMC_SR after CKGR_PLLBR is written
;// <o5.14..15> OUTB: PLL B Clock Frequency Range
;// <0=> 80 .. 160MHz <1=> Reserved
;// <2=> 150 .. 240MHz <3=> Reserved
;// <o5.16..26> MULB: PLL B Multiplier <0-2047>
;// <i> 0 - The PLL B is deactivated
;// <i> 1 .. 2047 - The PLL B Clock frequency is the PLL a input
;// <i> frequency multiplied by MULB + 1
;// <o5.28> USB_96M: Divider by 2 Enable
;// <i> 0 - USB ports = PLL B Clock, PLL B Clock must be 48MHz
;// <i> 1 - USB ports = PLL B Clock / 2, PLL B Clock must be 96MHz
;// </h>
;//
;// <h> Master Clock Register (CKGR_MCKR)
;// <o6.0..1> CSS: Master Clock Selection
;// <0=> Slow Clock
;// <1=> Main Clock
;// <2=> PLL A Clock
;// <3=> PLL B Clock
;// <o6.2..4> PRES: Master Clock Prescaler
;// <0=> Clock <1=> Clock / 2
;// <2=> Clock / 4 <3=> Clock / 8
;// <4=> Clock / 16 <5=> Clock / 32
;// <6=> Clock / 64 <7=> Reserved
;// <o6.8..9> MDIV: Master Clock Division
;// <0=> Processor Clock = Master Clock
;// <1=> Processor Clock = Master Clock / 2
;// <2=> Processor Clock = Master Clock / 3
;// <3=> Processor Clock = Master Clock / 4
;// </h>
;//
;// <h> Programmable Clock Register 0 (PMC_PCK0)
;// <o7.0..1> CSS: Master Clock Selection
;// <0=> Slow Clock
;// <1=> Main Clock
;// <2=> PLL A Clock
;// <3=> PLL B Clock
;// <o7.2..4> PRES: Programmable Clock Prescaler
;// <0=> Clock <1=> Clock / 2
;// <2=> Clock / 4 <3=> Clock / 8
;// <4=> Clock / 16 <5=> Clock / 32
;// <6=> Clock / 64 <7=> Reserved
;// </h>
;//
;// <h> Programmable Clock Register 1 (PMC_PCK1)
;// <o8.0..1> CSS: Master Clock Selection
;// <0=> Slow Clock
;// <1=> Main Clock
;// <2=> PLL A Clock
;// <3=> PLL B Clock
;// <o8.2..4> PRES: Programmable Clock Prescaler
;// <0=> None <1=> Clock / 2
;// <2=> Clock / 4 <3=> Clock / 8
;// <4=> Clock / 16 <5=> Clock / 32
;// <6=> Clock / 64 <7=> Reserved
;// </h>
;//
;// <h> Programmable Clock Register 2 (PMC_PCK2)
;// <o9.0..1> CSS: Master Clock Selection
;// <0=> Slow Clock
;// <1=> Main Clock
;// <2=> PLL A Clock
;// <3=> PLL B Clock
;// <o9.2..4> PRES: Programmable Clock Prescaler
;// <0=> None <1=> Clock / 2
;// <2=> Clock / 4 <3=> Clock / 8
;// <4=> Clock / 16 <5=> Clock / 32
;// <6=> Clock / 64 <7=> Reserved
;// </h>
;//
;// <h> Programmable Clock Register 3 (PMC_PCK3)
;// <o10.0..1> CSS: Master Clock Selection
;// <0=> Slow Clock
;// <1=> Main Clock
;// <2=> PLL A Clock
;// <3=> PLL B Clock
;// <o10.2..4> PRES: Programmable Clock Prescaler
;// <0=> None <1=> Clock / 2
;// <2=> Clock / 4 <3=> Clock / 8
;// <4=> Clock / 16 <5=> Clock / 32
;// <6=> Clock / 64 <7=> Reserved
;// </h>
;// </e>
PMC_SETUP EQU 1
PMC_SCER_Val EQU 0x00000001
PMC_PCER_Val EQU 0x00000018
CKGR_MOR_Val EQU 0x0000FF01
CKGR_PLLAR_Val EQU 0x2026BF04
CKGR_PLLBR_Val EQU 0x10483F0E
PMC_MCKR_Val EQU 0x00000202
PMC_PCK0_Val EQU 0x00000000
PMC_PCK1_Val EQU 0x00000000
PMC_PCK2_Val EQU 0x00000000
PMC_PCK3_Val EQU 0x00000000
; Cache
; Constants
ICACHE_ENABLE EQU (1<<12) ; Instruction Cache Enable Value
;// <e> Instruction Cache Enable
;// </e>
CACHE_SETUP EQU 1
PRESERVE8
; Area Definition and Entry Point
; Startup Code must be linked first at Address at which it expects to run.
AREA RESET, CODE, READONLY
ARM
; Exception Vectors
; Mapped to Address 0.
; Absolute addressing mode must be used.
; Dummy Handlers are implemented as infinite loops which can be modified.
Vectors LDR PC,Reset_Addr
LDR PC,Undef_Addr
LDR PC,SWI_Addr
LDR PC,PAbt_Addr
LDR PC,DAbt_Addr
NOP ; Reserved Vector
; LDR PC,IRQ_Addr
LDR PC,[PC,#-0xF20] ; Vector From AIC_IVR
; LDR PC,FIQ_Addr
LDR PC,[PC,#-0xF20] ; Vector From AIC_FVR
Reset_Addr DCD Reset_Handler
Undef_Addr DCD Undef_Handler
SWI_Addr DCD SWI_Handler
PAbt_Addr DCD PAbt_Handler
DAbt_Addr DCD DAbt_Handler
DCD 0 ; Reserved Address
IRQ_Addr DCD IRQ_Handler
FIQ_Addr DCD FIQ_Handler
Undef_Handler B Undef_Handler
SWI_Handler B SWI_Handler
PAbt_Handler B PAbt_Handler
DAbt_Handler B DAbt_Handler
IRQ_Handler B IRQ_Handler
FIQ_Handler B FIQ_Handler
; Reset Handler
EXPORT Reset_Handler
Reset_Handler
; Setup External Bus Interface (EBI)
IF EBI_SETUP != 0
; Setup Static Memory Controller if enabled
LDR R0, =SMC_BASE
IF SMC_CSR0_SETUP != 0
LDR R1, =SMC_CSR0_Val
STR R1, [R0, #SMC_CSR0_OFS]
ENDIF
IF SMC_CSR1_SETUP != 0
LDR R1, =SMC_CSR1_Val
STR R1, [R0, #SMC_CSR1_OFS]
ENDIF
IF SMC_CSR2_SETUP != 0
LDR R1, =SMC_CSR2_Val
STR R1, [R0, #SMC_CSR2_OFS]
ENDIF
IF SMC_CSR3_SETUP != 0
LDR R1, =SMC_CSR3_Val
STR R1, [R0, #SMC_CSR3_OFS]
ENDIF
IF SMC_CSR4_SETUP != 0
LDR R1, =SMC_CSR4_Val
STR R1, [R0, #SMC_CSR4_OFS]
ENDIF
IF SMC_CSR5_SETUP != 0
LDR R1, =SMC_CSR5_Val
STR R1, [R0, #SMC_CSR5_OFS]
ENDIF
IF SMC_CSR6_SETUP != 0
LDR R1, =SMC_CSR6_Val
STR R1, [R0, #SMC_CSR6_OFS]
ENDIF
IF SMC_CSR7_SETUP != 0
LDR R1, =SMC_CSR7_Val
STR R1, [R0, #SMC_CSR7_OFS]
ENDIF
; Enable EBI Chip Select assignments if necessary
IF EBI_CFG_SETUP != 0
LDR R0, =EBI_BASE
LDR R1, =EBI_CSA_Val
STR R1, [R0, #EBI_CSA_OFS]
LDR R1, =EBI_CFGR_Val
STR R1, [R0, #EBI_CFGR_OFS]
ENDIF
; Setup SDRAM Controller if enabled
IF :DEF:NO_SDRAM_INIT
ELSE
IF SDRAMC_SETUP != 0
; Setup Parallel Input/Output C Registers
; for driving SDRAM lines
LDR R0, =PIOC_BASE
LDR R1, =0xFFFF0000
STR R1, [R0, #PIO_PDR_OFS]
LDR R0, =SDRAMC_BASE
LDR R2, =EBI_CS1_ADDRESS
MOV R3, #0
; Write All Banks Precharge Command to SDRAM
MOV R1, #PRCGALL_CMD
STR R1, [R0, #SDRAMC_MR_OFS]
STR R3, [R2, #0]
; Provide 8 Auto Refresh to SDRAM
MOV R1, #RFSH_CMD
STR R1, [R0, #SDRAMC_MR_OFS]
STR R3, [R2, #0]
STR R3, [R2, #0]
STR R3, [R2, #0]
STR R3, [R2, #0]
STR R3, [R2, #0]
STR R3, [R2, #0]
STR R3, [R2, #0]
STR R3, [R2, #0]
; Write a Load Mode Register Command to SDRAM
MOV R1, #LMR_CMD
STR R1, [R0, #SDRAMC_MR_OFS]
STR R3, [R2, #0x80]
; Setup Refresh Timer Register
LDR R1, =SDRAMC_TR_Val
STR R1, [R0, #SDRAMC_TR_OFS]
STR R3, [R2, #0]
; Setup SDRAM Controller Registers
LDR R1, =SDRAMC_CR_Val
STR R1, [R0, #SDRAMC_CR_OFS]
LDR R1, =SDRAMC_SRR_Val
STR R1, [R0, #SDRAMC_SRR_OFS]
LDR R1, =SDRAMC_IER_Val
STR R1, [R0, #SDRAMC_IER_OFS]
ENDIF
ENDIF ; of IF :DEF:NO_SDRAM_INIT
; Setup Burst Flash Controller if enabled
IF BFC_SETUP != 0
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