📄 dn_v21.mdl
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XIncr "1.0"
XLabel "Samples"
YUnits "dB"
YMin "-166.170916393846"
YMax "46.3976819110496"
YLabel "Magnitude-squared, dB"
LineProperties off
wintypeSpecScope "Hann"
RsSpecScope "50"
betaSpecScope "5"
winsampSpecScope "Periodic"
}
Block {
BlockType SubSystem
Name "resampler_dn"
Ports [4, 5]
Position [515, 302, 620, 488]
BackgroundColor "darkGreen"
TreatAsAtomicUnit off
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
MaskHideContents off
System {
Name "resampler_dn"
Location [2, 82, 1270, 973]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "88"
Block {
BlockType Inport
Name "data"
Position [130, 253, 160, 267]
IconDisplay "Port number"
}
Block {
BlockType Inport
Name "L"
Position [130, 468, 160, 482]
Port "2"
IconDisplay "Port number"
}
Block {
BlockType Inport
Name "phase"
Position [130, 518, 160, 532]
Port "3"
IconDisplay "Port number"
}
Block {
BlockType Inport
Name "valid_in"
Position [130, 658, 160, 672]
Port "4"
IconDisplay "Port number"
}
Block {
BlockType Reference
Name " System Generator"
Tag "genX"
Ports []
Position [437, 763, 488, 813]
ShowName off
AttributesFormatString "System\\nGenerator"
UserDataPersistent on
UserData "DataTag2"
SourceBlock "xbsIndex_r4/ System Generator"
SourceType "Xilinx System Generator Block"
ShowPortLabels on
infoedit " System Generator"
xilinxfamily "Spartan3"
part "xc3s5000"
speed "-4"
package "fg900"
synthesis_tool "XST"
directory "./netlist"
testbench off
simulink_period "1"
sysclk_period "1.000000e+001"
incr_netlist off
trim_vbits "Everywhere in SubSystem"
dbl_ovrd "According to Block Masks"
core_generation "According to Block Masks"
run_coregen off
deprecated_control off
eval_field "0"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "sysgen"
block_version "8.2"
sg_icon_stat "51,50,-1,-1,red,beige,0,07734"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');"
"\npatch([0 51 51 0 ],[0 0 50 50 ],[0.93 0.92 0.86]);\npatch([12 4 16 4 12 25 "
"29 33 47 36 25 17 29 17 25 36 47 33 29 25 12 ],[5 13 25 37 45 45 41 45 45 34 "
"45 37 25 13 5 16 5 5 9 5 5 ],[0.6 0.2 0.25]);\nplot([0 0 51 51 0 ],[0 50 50 0"
" 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin"
" icon text');\nfprintf('','COMMENT: end icon text');\n"
sg_blockgui_xml "<!-- * Copyright (c) 2005, Xilinx, Inc. "
"All Rights Reserved. --><!-- * Reproduction or reuse, in any for"
"m, without the explicit written --><!-- * consent of Xilinx, Inc., is stri"
"ctly prohibited. --><sysgenblock has_userdata=\"true\" tag="
"\"genX\" block_type=\"sysgen\" simulinkname=\" System Generator\" >\n <icon w"
"idth=\"51\" bg_color=\"beige\" height=\"50\" caption_format=\"System\\nGenera"
"tor\" wmark_color=\"red\" />\n <callbacks DeleteFcn=\"xlSysgenGUI('delete', g"
"cs, gcbh);\" OpenFcn=\"xlSysgenGUI('startup',gcs,gcbh)\" ModelCloseFcn=\"xlSy"
"sgenGUI('Close',gcs,gcbh)\" PostSaveFcn=\"xlSysgenGUI('Save')\" />\n <librari"
"es>\n <library name=\"xbsIndex\" />\n <library name=\"xbsBasic\" />\n <lib"
"rary name=\"xbsTools\" />\n </libraries>\n <subsystem_model file=\"system_gen"
"erator_subsystem.mdl\" />\n <blockgui label=\"Xilinx System Generator\" >\n "
"<editbox evaluate=\"false\" multi_line=\"true\" name=\"infoedit\" read_only="
"\"true\" default=\" System Generator\" />\n <editbox evaluate=\"false\" name"
"=\"xilinxfamily\" default=\"Virtex4\" label=\"Xilinx family\" />\n <editbox "
"evaluate=\"false\" name=\"part\" default=\"xc4vsx35\" label=\"Part\" />\n <e"
"ditbox evaluate=\"false\" name=\"speed\" default=\"-10\" label=\"Speed\" />\n"
" <editbox evaluate=\"false\" name=\"package\" default=\"ff668\" label=\"Pack"
"age\" />\n <listbox evaluate=\"true\" name=\"synthesis_tool\" default=\"XST"
"\" label=\"Synthesis tool\" >\n <item value=\"Spectrum\" />\n <item value"
"=\"Synplify\" />\n <item value=\"Synplify Pro\" />\n <item value=\"XST\" "
"/>\n <item value=\"Precision\" />\n </listbox>\n <editbox evaluate=\"fals"
"e\" name=\"directory\" default=\"./netlist\" label=\"Target directory\" />\n "
" <checkbox evaluate=\"true\" name=\"testbench\" default=\"off\" label=\"Testb"
"ench\" />\n <editbox evaluate=\"true\" name=\"simulink_period\" default=\"1"
"\" label=\"Simulink period\" />\n <editbox evaluate=\"true\" name=\"sysclk_p"
"eriod\" default=\"10\" label=\"System clock period\" />\n <checkbox evaluate"
"=\"true\" name=\"incr_netlist\" default=\"off\" label=\"Incremental netlistin"
"g\" />\n <listbox evaluate=\"true\" name=\"trim_vbits\" default=\"Everywhere"
" in SubSystem\" label=\"Trim valid bits\" >\n <item value=\"According to Bl"
"ock Masks\" />\n <item value=\"Everywhere in SubSystem\" />\n <item value"
"=\"No Where in SubSystem\" />\n </listbox>\n <listbox evaluate=\"true\" nam"
"e=\"dbl_ovrd\" default=\"According to Block Masks\" label=\"Override with dou"
"bles\" >\n <item value=\"According to Block Masks\" />\n <item value=\"Ev"
"erywhere in SubSystem\" />\n <item value=\"No Where in SubSystem\" />\n </"
"listbox>\n <listbox evaluate=\"true\" name=\"core_generation\" default=\"Acc"
"ording to Block Masks\" label=\"Generate cores\" >\n <item value=\"Accordin"
"g to Block Masks\" />\n <item value=\"Everywhere Available\" />\n <item v"
"alue=\"Not Needed - Already Generated\" />\n </listbox>\n <checkbox evaluat"
"e=\"true\" name=\"run_coregen\" default=\"off\" label=\"Run CoreGen\" />\n <"
"checkbox evaluate=\"true\" name=\"deprecated_control\" default=\"off\" label="
"\"Show deprecated controls\" />\n <hiddenvar evaluate=\"true\" name=\"eval_f"
"ield\" default=\"0\" />\n </blockgui>\n</sysgenblock>\n"
}
Block {
BlockType Reference
Name "Constant5"
Ports [0, 1]
Position [675, 399, 720, 421]
SourceBlock "xbsIndex_r4/Constant"
SourceType "Xilinx Constant Block Block"
arith_type "Unsigned"
const "(2^(num_bits-bin_pt))-1"
n_bits "num_bits-bin_pt"
bin_pt "0"
explicit_period off
period "1"
dsp48_infoedit "The use of this block for DSP48 instruction"
"s is deprecated. Please use the Opmode block."
equ "P=C"
opselect "C"
inp2 "PCIN>>17"
opr "+"
inp1 "P"
carry "CIN"
dbl_ovrd off
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "constant"
block_version "VER_STRING_GOES_HERE"
sg_icon_stat "45,22,0,1,white,blue,0,153fad44"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');"
"\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 2"
"7 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17"
" 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 0 55 55 0 ],[0 26 26 "
"0 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begi"
"n icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COMME"
"NT: end icon text');\n"
}
Block {
BlockType Reference
Name "Expression"
Ports [3, 1]
Position [760, 465, 810, 515]
SourceBlock "xbsIndex_r4/Expression"
SourceType "Xilinx Bitwise Expression Evaluator Block"
expression "a ^ b"
align_bp on
en on
latency "1"
precision "Full"
arith_type "Unsigned"
n_bits "8"
bin_pt "2"
dbl_ovrd off
xl_use_area off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "expr"
block_version "VER_STRING_GOES_HERE"
sg_icon_stat "50,50,3,1,white,blue,0,e9a73637"
sg_mask_display "fprintf('','COMMENT: begin icon graphics ')"
";\npatch([0 50 50 0 ],[0 0 50 50 ],[0.77 0.82 0.91]);\npatch([11 3 15 3 11 24"
" 28 32 46 35 24 16 28 16 24 35 46 32 28 24 11 ],[5 13 25 37 45 45 41 45 45 34"
" 45 37 25 13 5 16 5 5 9 5 5 ],[0.98 0.96 0.92]);\nplot([0 0 50 50 0 ],[0 50 5"
"0 0 0 ]);\nfprintf('','COMMENT: end icon graphics');\n\nfprintf('','COMMENT: "
"begin icon text ');\ncolor('black');port_label('input',1,'a');\ncolor('black'"
");port_label('input',2,'b');\ncolor('black');port_label('input',3,'en');\ncol"
"or('black');disp('a ^ b');\nfprintf('','COMMENT: end icon text');\n"
}
Block {
BlockType Reference
Name "L_value"
Ports [1, 1]
Position [185, 464, 240, 486]
SourceBlock "xbsIndex_r4/Gateway In"
SourceType "Xilinx Gateway In Block"
infoedit "Gateway in block. Converts inputs of type "
"Simulink integer, double and fixed point to Xilinx fixed point type.<P><P>Ha"
"rdware notes: In hardware these blocks become top level input ports."
arith_type "Unsigned"
n_bits "num_bits"
bin_pt "bin_pt-1"
quantization "Round (unbiased: +/- Inf)"
overflow "Saturate"
period "1"
dbl_ovrd off
timing_constraint "None"
locs_specified off
LOCs "{}"
xl_use_area off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
has_advanced_control "0"
sggui_pos "20,20,356,423"
block_type "gatewayin"
block_version "VER_STRING_GOES_HERE"
sg_icon_stat "55,22,1,1,white,yellow,0,4bb76ffd"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');"
"\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 3"
"2 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14"
" 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 0 65 65 0 ],[0 20 20 "
"0 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begi"
"n icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In "
"','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','C"
"OMMENT: end icon text');\n"
}
Block {
BlockType Reference
Name "Register1"
Ports [2, 1]
Position [765, 553, 810, 602]
SourceBlock "xbsIndex_r4/Register"
SourceType "Xilinx Register Block"
init "0"
rst off
en on
dbl_ovrd off
xl_use_area off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "register"
block_version "VER_STRING_GOES_HERE"
sg_icon_stat "45,49,2,1,white,blue,0,cc3303a0"
sg_mask_display "fprintf('','COMMENT: begin icon graphics ')"
";\npatch([0 45 45 0 ],[0 0 49 49 ],[0.77 0.82 0.91]);\npatch([10 3 14 3 10 22"
" 25 28 41 31 21 14 25 14 21 31 41 28 25 22 10 ],[7 14 25 36 43 43 40 43 43 33"
" 43 36 25 14 7 17 7 7 10 7 7 ],[0.98 0.96 0.92]);\nplot([0 0 45 45 0 ],[0 49 "
"49 0 0 ]);\nfprintf('','COMMENT: end icon graphics');\n\nfprintf('','COMMENT:"
" begin icon text ');\ncolor('black');port_label('input',1,'d');\ncolor('black"
"');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\nc"
"olor('black');disp('\\bf{z^{-1}}','texmode','on');\nfprintf('','COMMENT: end "
"icon text');\n"
}
Block {
BlockType SubSystem
Name "addr_gen"
Ports [3, 2]
Position [590, 448, 675, 602]
TreatAsAtomicUnit off
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
MaskHideContents off
System {
Name "addr_gen"
Location [2, 82, 1270, 956]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "100"
Block {
BlockType Inport
Name "delta"
Position [180, 333, 210, 347]
IconDisplay "Port number"
}
Block {
BlockType Inport
Name "phase"
Position [180, 573, 210, 587]
Port "2"
IconDisplay "Port number"
}
Block {
BlockType Inport
Name "ce"
Position [180, 513, 210, 527]
Port "3"
IconDisplay "Port number"
}
Block {
BlockType Reference
Name "AddSub1"
Ports [3, 1]
Position [990, 307, 1040, 383]
SourceBlock "xbsIndex_r4/AddSub"
SourceType "Xilinx Adder/Subtractor Block"
mode "Addition"
use_carryin off
use_carryout off
en on
latency "1"
precision "User Defined"
arith_type "Unsigned"
n_bits "num_bits-bin_pt"
bin_pt "0"
quantization "Truncate"
overflow "Wrap"
dbl_ovrd off
use_behavioral_HDL on
pipelined off
use_rpm on
xl_use_area off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "addsub"
block_version "VER_STRING_GOES_HERE"
sg_icon_stat "50,76,3,1,white,blue,0,727db747"
sg_mask_display "fprintf('','COMMENT: begin icon graphic"
"s');\npatch([0 60 60 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([15 5 19 5 15"
" 30 34 38 54 41 29 20 34 20 29 41 54 38 34 30 15 ],[6 16 30 44 54 54 50 54 54"
" 41 53 44 30 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 0 60 60 0 ],[0 "
"58 58 0 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT"
": begin icon text');\ncolor('black');port_label('input',1,'a');\ncolor('black"
"');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a +"
" b}','texmode','on');\nfprintf('','COMMENT: end icon text');\n"
}
Block {
BlockType Reference
Name "AddSub3"
Ports [2, 1]
Position [330, 285, 380, 360]
SourceBlock "xbsIndex_r4/AddSub"
SourceType "Xilinx Adder/Subtractor Block"
mode "Addition"
use_carryin off
use_carryout off
en off
latency "0"
precision "User Defined"
arith_type "Unsigned"
n_bits "num_bits+1"
bin_pt "bin_pt"
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