📄 dn_v2.mdl
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"inxfamily\" default=\"Virtex4\" label=\"Xilinx family\" />\n <editbox evalua"
"te=\"false\" name=\"part\" default=\"xc4vsx35\" label=\"Part\" />\n <editbox"
" evaluate=\"false\" name=\"speed\" default=\"-10\" label=\"Speed\" />\n <edi"
"tbox evaluate=\"false\" name=\"package\" default=\"ff668\" label=\"Package\" "
"/>\n <listbox evaluate=\"true\" name=\"synthesis_tool\" default=\"XST\" labe"
"l=\"Synthesis tool\" >\n <item value=\"Spectrum\" />\n <item value=\"Synp"
"lify\" />\n <item value=\"Synplify Pro\" />\n <item value=\"XST\" />\n "
"<item value=\"Precision\" />\n </listbox>\n <editbox evaluate=\"false\" nam"
"e=\"directory\" default=\"./netlist\" label=\"Target directory\" />\n <check"
"box evaluate=\"true\" name=\"testbench\" default=\"off\" label=\"Testbench\" "
"/>\n <editbox evaluate=\"true\" name=\"simulink_period\" default=\"1\" label"
"=\"Simulink period\" />\n <editbox evaluate=\"true\" name=\"sysclk_period\" "
"default=\"10\" label=\"System clock period\" />\n <checkbox evaluate=\"true"
"\" name=\"incr_netlist\" default=\"off\" label=\"Incremental netlisting\" />"
"\n <listbox evaluate=\"true\" name=\"trim_vbits\" default=\"Everywhere in Su"
"bSystem\" label=\"Trim valid bits\" >\n <item value=\"According to Block Ma"
"sks\" />\n <item value=\"Everywhere in SubSystem\" />\n <item value=\"No "
"Where in SubSystem\" />\n </listbox>\n <listbox evaluate=\"true\" name=\"db"
"l_ovrd\" default=\"According to Block Masks\" label=\"Override with doubles\""
" >\n <item value=\"According to Block Masks\" />\n <item value=\"Everywhe"
"re in SubSystem\" />\n <item value=\"No Where in SubSystem\" />\n </listbo"
"x>\n <listbox evaluate=\"true\" name=\"core_generation\" default=\"According"
" to Block Masks\" label=\"Generate cores\" >\n <item value=\"According to B"
"lock Masks\" />\n <item value=\"Everywhere Available\" />\n <item value="
"\"Not Needed - Already Generated\" />\n </listbox>\n <checkbox evaluate=\"t"
"rue\" name=\"run_coregen\" default=\"off\" label=\"Run CoreGen\" />\n <check"
"box evaluate=\"true\" name=\"deprecated_control\" default=\"off\" label=\"Sho"
"w deprecated controls\" />\n <hiddenvar evaluate=\"true\" name=\"eval_field"
"\" default=\"0\" />\n </blockgui>\n</sysgenblock>\n"
}
Block {
BlockType Constant
Name "Constant1"
Position [60, 360, 105, 390]
Value "32*0.8*2^-2"
}
Block {
BlockType Constant
Name "Constant2"
Position [70, 450, 100, 480]
}
Block {
BlockType Constant
Name "Constant3"
Position [175, 405, 225, 435]
Value "0"
}
Block {
BlockType Display
Name "Display1"
Ports [1]
Position [1210, 555, 1300, 585]
Decimation "1"
Lockdown off
SampleTime "1"
}
Block {
BlockType Display
Name "Display2"
Ports [1]
Position [1145, 620, 1260, 650]
Format "long"
Decimation "1"
Lockdown off
}
Block {
BlockType Display
Name "Display3"
Ports [1]
Position [1145, 494, 1260, 526]
Format "long"
Decimation "1"
Lockdown off
}
Block {
BlockType Product
Name "Divide"
Ports [2, 1]
Position [1150, 551, 1180, 584]
Inputs "*/"
OutDataTypeMode "double"
OutScaling "2^-10"
RndMeth "Floor"
SaturateOnIntegerOverflow off
}
Block {
BlockType SubSystem
Name "Enabled\nSubsystem"
Ports [0, 1, 1]
Position [990, 489, 1090, 531]
TreatAsAtomicUnit on
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
MaskHideContents off
System {
Name "Enabled\nSubsystem"
Location [421, 301, 919, 601]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "100"
Block {
BlockType EnablePort
Name "Enable"
Ports []
Position [235, 20, 255, 40]
}
Block {
BlockType Reference
Name "Counter\nFree-Running"
Ports [0, 1]
Position [190, 95, 220, 125]
SourceBlock "simulink/Sources/Counter\nFree-Running"
SourceType "Counter Free-Running"
ShowPortLabels on
NumBits "32"
tsamp "1"
}
Block {
BlockType Outport
Name "Out1"
Position [360, 103, 390, 117]
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "Counter\nFree-Running"
SrcPort 1
DstBlock "Out1"
DstPort 1
}
}
}
Block {
BlockType SubSystem
Name "Enabled\nSubsystem1"
Ports [0, 1, 1]
Position [990, 614, 1090, 656]
TreatAsAtomicUnit on
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
MaskHideContents off
System {
Name "Enabled\nSubsystem1"
Location [421, 301, 919, 601]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "100"
Block {
BlockType EnablePort
Name "Enable"
Ports []
Position [235, 20, 255, 40]
}
Block {
BlockType Reference
Name "Counter\nFree-Running"
Ports [0, 1]
Position [190, 95, 220, 125]
SourceBlock "simulink/Sources/Counter\nFree-Running"
SourceType "Counter Free-Running"
ShowPortLabels on
NumBits "32"
tsamp "1"
}
Block {
BlockType Outport
Name "Out1"
Position [360, 103, 390, 117]
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "Counter\nFree-Running"
SrcPort 1
DstBlock "Out1"
DstPort 1
}
}
}
Block {
BlockType SubSystem
Name "Enabled\ncapture"
Ports [1, 0, 1]
Position [775, 384, 875, 426]
TreatAsAtomicUnit on
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
MaskHideContents off
System {
Name "Enabled\ncapture"
Location [277, 268, 775, 568]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "100"
Block {
BlockType Inport
Name "In1"
Position [185, 103, 215, 117]
IconDisplay "Port number"
}
Block {
BlockType EnablePort
Name "Enable"
Ports []
Position [235, 20, 255, 40]
}
Block {
BlockType ToWorkspace
Name "To Workspace"
Position [355, 95, 415, 125]
VariableName "filter_out"
MaxDataPoints "inf"
SampleTime "-1"
SaveFormat "Array"
}
Line {
SrcBlock "In1"
SrcPort 1
DstBlock "To Workspace"
DstPort 1
}
}
}
Block {
BlockType DiscretePulseGenerator
Name "Pulse\nGenerator1"
Ports [0, 1]
Position [75, 613, 120, 647]
Period "10"
PulseWidth "4"
}
Block {
BlockType Scope
Name "Scope1"
Ports [2]
Position [950, 536, 980, 569]
Floating off
Location [5, 34, 1089, 605]
Open off
NumInputPorts "2"
ZoomMode "xonly"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
axes2 "%<SignalLabel>"
}
TimeRange "1000"
YMin "0~0"
YMax "512~5"
SaveName "ScopeData1"
DataFormat "StructureWithTime"
SampleTime "0"
}
Block {
BlockType Scope
Name "Scope2"
Ports [4]
Position [985, 271, 1015, 334]
Floating off
Location [220, 256, 1134, 841]
Open off
NumInputPorts "4"
ZoomMode "yonly"
List {
ListType AxesTitles
axes1 "Input Signal"
axes2 "Decimated Output Signal"
axes3 "Coefficient Address"
axes4 "Valid Out"
}
TimeRange "151.7231833910034"
YMin "-0.99~-64~75~-1"
YMax "-0.955~64~120~2"
SaveName "ScopeData2"
DataFormat "StructureWithTime"
LimitDataPoints off
SampleTime "0"
}
Block {
BlockType SubSystem
Name "resampler_dn"
Ports [4, 5]
Position [515, 302, 620, 488]
BackgroundColor "darkGreen"
TreatAsAtomicUnit off
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
MaskHideContents off
System {
Name "resampler_dn"
Location [2, 82, 1270, 973]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "88"
Block {
BlockType Inport
Name "data"
Position [130, 253, 160, 267]
IconDisplay "Port number"
}
Block {
BlockType Inport
Name "L"
Position [130, 468, 160, 482]
Port "2"
IconDisplay "Port number"
}
Block {
BlockType Inport
Name "phase"
Position [130, 518, 160, 532]
Port "3"
IconDisplay "Port number"
}
Block {
BlockType Inport
Name "valid_in"
Position [130, 658, 160, 672]
Port "4"
IconDisplay "Port number"
}
Block {
BlockType Reference
Name " System Generator"
Tag "genX"
Ports []
Position [437, 763, 488, 813]
ShowName off
AttributesFormatString "System\\nGenerator"
UserDataPersistent on
UserData "DataTag1"
SourceBlock "xbsIndex_r4/ System Generator"
SourceType "Xilinx System Generator Block"
ShowPortLabels on
infoedit " System Generator"
xilinxfamily "Spartan3"
part "xc3s5000"
speed "-4"
package "fg900"
synthesis_tool "XST"
directory "./netlist"
testbench off
simulink_period "1"
sysclk_period "1.000000e+001"
incr_netlist off
trim_vbits "Everywhere in SubSystem"
dbl_ovrd "According to Block Masks"
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