📄 frac_resampler_dn_v2.mdl
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}
Block {
BlockType Scope
Name "Scope"
Ports [2]
Position [1230, 266, 1260, 299]
Floating off
Location [188, 390, 873, 903]
Open off
NumInputPorts "2"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
axes2 "%<SignalLabel>"
}
YMin "-5~-5"
YMax "5~5"
DataFormat "StructureWithTime"
SampleTime "0"
}
Block {
BlockType Reference
Name "Slice"
Ports [1, 1]
Position [570, 291, 615, 319]
SourceBlock "xbsIndex_r4/Slice"
SourceType "Xilinx Bit Slice Extractor Block"
infoedit "Extracts a given range of bits from eac"
"h input sample and presents it at the output. The output type is ordinarily "
"unsigned with binary point at zero, but can be Boolean when the slice is one "
"bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
nbits "num_bits"
boolean_output "off"
mode "Lower Bit Location + Width"
bit1 "1"
base1 "MSB of Input"
bit0 "0"
base0 "LSB of Input"
dbl_ovrd "off"
has_advanced_control "0"
sggui_pos "20,20,449,389"
block_type "slice"
block_version "VER_STRING_GOES_HERE"
sg_icon_stat "45,28,1,1,white,blue,0,fe24a11e"
sg_mask_display "fprintf('','COMMENT: begin icon graphic"
"s ');\npatch([0 45 45 0 ],[0 0 28 28 ],[0.77 0.82 0.91]);\npatch([15 10 17 10"
" 15 22 24 26 34 28 22 18 26 18 22 28 34 26 24 22 15 ],[3 8 15 22 27 27 25 27 "
"27 21 27 23 15 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 0 45 45 0 ],[0 2"
"8 28 0 0 ]);\nfprintf('','COMMENT: end icon graphics');\n\nfprintf('','COMMEN"
"T: begin icon text ');\ncolor('black');port_label('output',1,'[a:b]');\nfprin"
"tf('','COMMENT: end icon text');\n"
}
Block {
BlockType Reference
Name "Slice1"
Ports [1, 1]
Position [570, 406, 615, 434]
SourceBlock "xbsIndex_r4/Slice"
SourceType "Xilinx Bit Slice Extractor Block"
infoedit "Extracts a given range of bits from eac"
"h input sample and presents it at the output. The output type is ordinarily "
"unsigned with binary point at zero, but can be Boolean when the slice is one "
"bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
nbits "1"
boolean_output "on"
mode "Upper Bit Location + Width"
bit1 "0"
base1 "MSB of Input"
bit0 "0"
base0 "LSB of Input"
dbl_ovrd "off"
has_advanced_control "0"
sggui_pos "20,20,449,389"
block_type "slice"
block_version "VER_STRING_GOES_HERE"
sg_icon_stat "45,28,1,1,white,blue,0,fe24a11e"
sg_mask_display "fprintf('','COMMENT: begin icon graphic"
"s ');\npatch([0 45 45 0 ],[0 0 28 28 ],[0.77 0.82 0.91]);\npatch([15 10 17 10"
" 15 22 24 26 34 28 22 18 26 18 22 28 34 26 24 22 15 ],[3 8 15 22 27 27 25 27 "
"27 21 27 23 15 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 0 45 45 0 ],[0 2"
"8 28 0 0 ]);\nfprintf('','COMMENT: end icon graphics');\n\nfprintf('','COMMEN"
"T: begin icon text ');\ncolor('black');port_label('output',1,'[a:b]');\nfprin"
"tf('','COMMENT: end icon text');\n"
}
Block {
BlockType Reference
Name "Slice2"
Ports [1, 1]
Position [850, 306, 895, 334]
SourceBlock "xbsIndex_r4/Slice"
SourceType "Xilinx Bit Slice Extractor Block"
infoedit "Extracts a given range of bits from eac"
"h input sample and presents it at the output. The output type is ordinarily "
"unsigned with binary point at zero, but can be Boolean when the slice is one "
"bit wide.<P><P>Hardware notes: In hardware this block costs nothing."
nbits "num_bits-bin_pt"
boolean_output "off"
mode "Upper Bit Location + Width"
bit1 "0"
base1 "MSB of Input"
bit0 "0"
base0 "LSB of Input"
dbl_ovrd "off"
has_advanced_control "0"
sggui_pos "20,20,449,398"
block_type "slice"
block_version "VER_STRING_GOES_HERE"
sg_icon_stat "45,28,1,1,white,blue,0,fe24a11e"
sg_mask_display "fprintf('','COMMENT: begin icon graphic"
"s ');\npatch([0 45 45 0 ],[0 0 28 28 ],[0.77 0.82 0.91]);\npatch([15 10 17 10"
" 15 22 24 26 34 28 22 18 26 18 22 28 34 26 24 22 15 ],[3 8 15 22 27 27 25 27 "
"27 21 27 23 15 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 0 45 45 0 ],[0 2"
"8 28 0 0 ]);\nfprintf('','COMMENT: end icon graphics');\n\nfprintf('','COMMEN"
"T: begin icon text ');\ncolor('black');port_label('output',1,'[a:b]');\nfprin"
"tf('','COMMENT: end icon text');\n"
}
Block {
BlockType Outport
Name "addr"
Position [1275, 338, 1305, 352]
IconDisplay "Port number"
BusOutputAsStruct off
}
Block {
BlockType Outport
Name "clk_div"
Position [1275, 443, 1305, 457]
Port "2"
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "Register"
SrcPort 1
Points [0, 0; 20, 0]
Branch {
Points [0, -125; -505, 0; 0, 110]
DstBlock "AddSub3"
DstPort 1
}
Branch {
DstBlock "Slice2"
DstPort 1
}
}
Line {
SrcBlock "delta"
SrcPort 1
Points [0, 0]
DstBlock "AddSub3"
DstPort 2
}
Line {
SrcBlock "ce"
SrcPort 1
Points [490, 0]
Branch {
Points [0, -75]
Branch {
Points [0, -115]
DstBlock "Register"
DstPort 2
}
Branch {
DstBlock "Register1"
DstPort 2
}
}
Branch {
Points [225, 0; 0, -60]
Branch {
Points [0, -90]
DstBlock "AddSub1"
DstPort 3
}
Branch {
DstBlock "Register2"
DstPort 2
}
}
}
Line {
SrcBlock "AddSub3"
SrcPort 1
Points [0, 0; 155, 0]
Branch {
Points [15, 0]
DstBlock "Slice"
DstPort 1
}
Branch {
Points [0, 95]
DstBlock "Slice1"
DstPort 1
}
}
Line {
SrcBlock "Slice"
SrcPort 1
DstBlock "Reinterpret"
DstPort 1
}
Line {
SrcBlock "Reinterpret"
SrcPort 1
DstBlock "Register"
DstPort 1
}
Line {
SrcBlock "Slice1"
SrcPort 1
DstBlock "Register1"
DstPort 1
}
Line {
SrcBlock "phase"
SrcPort 1
Points [700, 0; 0, -235]
DstBlock "AddSub1"
DstPort 2
}
Line {
SrcBlock "Register2"
SrcPort 1
Points [155, 0]
Branch {
DstBlock "clk_div"
DstPort 1
}
Branch {
Points [0, -160]
DstBlock "Scope"
DstPort 2
}
}
Line {
SrcBlock "Register1"
SrcPort 1
DstBlock "Register2"
DstPort 1
}
Line {
SrcBlock "Slice2"
SrcPort 1
DstBlock "AddSub1"
DstPort 1
}
Line {
SrcBlock "AddSub1"
SrcPort 1
Points [135, 0]
Branch {
DstBlock "addr"
DstPort 1
}
Branch {
Points [0, -70]
DstBlock "Scope"
DstPort 1
}
}
Annotation {
Name "Upcounter with Overflow"
Position [579, 81]
UseDisplayTextAsClickCallback off
}
Annotation {
Name "integer part"
Position [872, 288]
UseDisplayTextAsClickCallback off
}
Annotation {
Name "overflow"
Position [594, 390]
UseDisplayTextAsClickCallback off
}
}
}
Block {
BlockType Reference
Name "ce_in"
Ports [1, 1]
Position [185, 654, 240, 676]
SourceBlock "xbsIndex_r4/Gateway In"
SourceType "Xilinx Gateway In Block"
infoedit "Gateway in block. Converts inputs of type "
"Simulink integer, double and fixed point to Xilinx fixed point type.<P><P>Ha"
"rdware notes: In hardware these blocks become top level input ports."
arith_type "Boolean"
n_bits "8"
bin_pt "0"
quantization "Round (unbiased: +/- Inf)"
overflow "Saturate"
period "1"
dbl_ovrd off
timing_constraint "None"
locs_specified off
LOCs "{}"
xl_use_area off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "gatewayin"
block_version "VER_STRING_GOES_HERE"
sg_icon_stat "55,22,1,1,white,yellow,0,4bb76ffd"
sg_mask_display "fprintf('','COMMENT: begin icon graphics ')"
";\npatch([0 55 55 0 ],[0 0 22 22 ],[0.95 0.93 0.65]);\npatch([22 18 23 18 22 "
"28 30 32 38 33 28 25 31 25 28 33 38 32 30 28 22 ],[2 6 11 16 20 20 18 20 20 1"
"5 20 17 11 5 2 7 2 2 4 2 2 ],[0.98 0.96 0.92]);\nplot([0 0 55 55 0 ],[0 22 22"
" 0 0 ]);\nfprintf('','COMMENT: end icon graphics');\n\nfprintf('','COMMENT: b"
"egin icon text ');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf"
" In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('"
"','COMMENT: end icon text');\nfprintf('','COMMENT: Make no changes above this"
" line -- machine generated code. ');\n"
}
Block {
BlockType Reference
Name "ce_out"
Ports [1, 1]
Position [1220, 364, 1275, 386]
SourceBlock "xbsIndex_r4/Gateway Out"
SourceType "Xilinx Gateway Out Block"
infoedit "Gateway out block. Converts Xilinx fixed p"
"oint inputs into ouputs of type Simulink integer, double, or fixed point.<P><"
"P>Hardware notes: In hardware these blocks become top level output ports or "
"are discarded, depending on how they are configured."
hdl_port on
timing_constraint "None"
locs_specified off
LOCs "{}"
xl_use_area off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "gatewayout"
block_version "VER_STRING_GOES_HERE"
sg_icon_stat "55,22,1,1,white,yellow,0,f0cec300"
sg_mask_display "fprintf('','COMMENT: begin icon graphics ')"
";\npatch([0 55 55 0 ],[0 0 22 22 ],[0.95 0.93 0.65]);\npatch([22 18 23 18 22 "
"28 30 32 38 33 28 25 31 25 28 33 38 32 30 28 22 ],[2 6 11 16 20 20 18 20 20 1"
"5 20 17 11 5 2 7 2 2 4 2 2 ],[0.98 0.96 0.92]);\nplot([0 0 55 55 0 ],[0 22 22"
" 0 0 ]);\nfprintf('','COMMENT: end icon graphics');\n\nfprintf('','COMMENT: b"
"egin icon text ');\ncolor('black');port_label('input',1,' ');\ncolor('black')"
";port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf("
"'','COMMENT: end icon text');\nfprintf('','COMMENT: Make no changes above thi"
"s line -- machine generated code. ');\n"
}
Block {
BlockType Reference
Name "data_in"
Ports [1, 1]
Position [185, 249, 240, 271]
SourceBlock "xbsIndex_r4/Gateway In"
SourceType "Xilinx Gateway In Block"
infoedit "Gateway in block. Converts inputs of type "
"Simulink integer, double and fixed point to Xilinx fixed point type.<P><P>Ha"
"rdware notes: In hardware these blocks become top level input ports."
arith_type "Signed (2's comp)"
n_bits "data_num_bits"
bin_pt "data_bin_pt"
quantization "Round (unbiased: +/- Inf)"
overflow "Saturate"
period "1"
dbl_ovrd off
timing_constraint "None"
locs_specified off
LOCs "{}"
xl_use_area off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
has_advanced_control "0"
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