📄 frac_resampler_dn_v2.mdl
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}
Block {
BlockType Display
Name "Display3"
Ports [1]
Position [1755, 739, 1870, 771]
Format "long"
Decimation "1"
Lockdown off
}
Block {
BlockType Product
Name "Divide"
Ports [2, 1]
Position [1760, 796, 1790, 829]
Inputs "*/"
OutDataTypeMode "double"
OutScaling "2^-10"
RndMeth "Floor"
SaturateOnIntegerOverflow off
}
Block {
BlockType SubSystem
Name "Enabled\nSubsystem"
Ports [0, 1, 1]
Position [1600, 734, 1700, 776]
TreatAsAtomicUnit on
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
MaskHideContents off
System {
Name "Enabled\nSubsystem"
Location [421, 301, 919, 601]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "100"
Block {
BlockType EnablePort
Name "Enable"
Ports []
Position [235, 20, 255, 40]
}
Block {
BlockType Reference
Name "Counter\nFree-Running"
Ports [0, 1]
Position [190, 95, 220, 125]
SourceBlock "simulink/Sources/Counter\nFree-Running"
SourceType "Counter Free-Running"
ShowPortLabels "on"
SystemSampleTime "-1"
FunctionWithSeparateData "off"
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
NumBits "32"
tsamp "1"
}
Block {
BlockType Outport
Name "Out1"
Position [360, 103, 390, 117]
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "Counter\nFree-Running"
SrcPort 1
DstBlock "Out1"
DstPort 1
}
}
}
Block {
BlockType SubSystem
Name "Enabled\nSubsystem1"
Ports [0, 1, 1]
Position [1600, 859, 1700, 901]
TreatAsAtomicUnit on
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
MaskHideContents off
System {
Name "Enabled\nSubsystem1"
Location [421, 301, 919, 601]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "100"
Block {
BlockType EnablePort
Name "Enable"
Ports []
Position [235, 20, 255, 40]
}
Block {
BlockType Reference
Name "Counter\nFree-Running"
Ports [0, 1]
Position [190, 95, 220, 125]
SourceBlock "simulink/Sources/Counter\nFree-Running"
SourceType "Counter Free-Running"
ShowPortLabels "on"
SystemSampleTime "-1"
FunctionWithSeparateData "off"
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
NumBits "32"
tsamp "1"
}
Block {
BlockType Outport
Name "Out1"
Position [360, 103, 390, 117]
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "Counter\nFree-Running"
SrcPort 1
DstBlock "Out1"
DstPort 1
}
}
}
Block {
BlockType SubSystem
Name "Enabled\ncapture"
Ports [1, 0, 1]
Position [1385, 629, 1485, 671]
TreatAsAtomicUnit on
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
MaskHideContents off
System {
Name "Enabled\ncapture"
Location [277, 268, 775, 568]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "100"
Block {
BlockType Inport
Name "In1"
Position [185, 103, 215, 117]
IconDisplay "Port number"
}
Block {
BlockType EnablePort
Name "Enable"
Ports []
Position [235, 20, 255, 40]
}
Block {
BlockType ToWorkspace
Name "To Workspace"
Position [355, 95, 415, 125]
VariableName "filter_out"
MaxDataPoints "inf"
SampleTime "-1"
SaveFormat "Array"
}
Line {
SrcBlock "In1"
SrcPort 1
DstBlock "To Workspace"
DstPort 1
}
}
}
Block {
BlockType DiscretePulseGenerator
Name "Pulse\nGenerator1"
Ports [0, 1]
Position [685, 753, 730, 787]
Period "10"
PulseWidth "4"
}
Block {
BlockType Scope
Name "Scope1"
Ports [2]
Position [1560, 781, 1590, 814]
Floating off
Location [159, 389, 1243, 960]
Open off
NumInputPorts "2"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
axes2 "%<SignalLabel>"
}
TimeRange "1000"
YMin "0~0"
YMax "512~5"
SaveName "ScopeData1"
DataFormat "StructureWithTime"
SampleTime "0"
}
Block {
BlockType Scope
Name "Scope2"
Ports [4]
Position [1595, 516, 1625, 579]
Floating off
Location [5, 34, 919, 619]
Open off
NumInputPorts "4"
ZoomMode "yonly"
List {
ListType AxesTitles
axes1 "Input Signal"
axes2 "Decimated Output Signal"
axes3 "Coefficient Address"
axes4 "Valid Out"
}
TimeRange "18.91695501730103"
YMin "-0.99~-64~75~-1"
YMax "-0.955~64~120~2"
SaveName "ScopeData2"
DataFormat "StructureWithTime"
LimitDataPoints off
SampleTime "0"
}
Block {
BlockType SubSystem
Name "resampler_dn"
Ports [4, 5]
Position [1125, 547, 1230, 733]
BackgroundColor "darkGreen"
TreatAsAtomicUnit off
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
MaskHideContents off
System {
Name "resampler_dn"
Location [0, 82, 1251, 982]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "112"
Block {
BlockType Inport
Name "data"
Position [130, 253, 160, 267]
IconDisplay "Port number"
}
Block {
BlockType Inport
Name "L"
Position [130, 468, 160, 482]
Port "2"
IconDisplay "Port number"
}
Block {
BlockType Inport
Name "phase"
Position [130, 518, 160, 532]
Port "3"
IconDisplay "Port number"
}
Block {
BlockType Inport
Name "valid_in"
Position [130, 658, 160, 672]
Port "4"
IconDisplay "Port number"
}
Block {
BlockType Reference
Name " System Generator"
Tag "genX"
Ports []
Position [437, 763, 488, 813]
ShowName off
AttributesFormatString "System\\nGenerator"
UserDataPersistent on
UserData "DataTag1"
SourceBlock "xbsIndex_r4/ System Generator"
SourceType "Xilinx System Generator Block"
ShowPortLabels on
infoedit " System Generator"
xilinxfamily "Virtex4"
part "xc4vsx25"
speed "-10"
package "ff668"
synthesis_tool "XST"
directory "./netlist"
testbench off
simulink_period "1"
sysclk_period "5.000000e+000"
incr_netlist off
trim_vbits "Everywhere in SubSystem"
dbl_ovrd "According to Block Masks"
core_generation "According to Block Masks"
run_coregen off
deprecated_control off
eval_field "0"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "sysgen"
block_version "8.2"
sg_icon_stat "51,50,-1,-1,red,beige,0,07734"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');"
"\npatch([0 51 51 0 ],[0 0 50 50 ],[0.93 0.92 0.86]);\npatch([12 4 16 4 12 25 "
"29 33 47 36 25 17 29 17 25 36 47 33 29 25 12 ],[5 13 25 37 45 45 41 45 45 34 "
"45 37 25 13 5 16 5 5 9 5 5 ],[0.6 0.2 0.25]);\nplot([0 0 51 51 0 ],[0 50 50 0"
" 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin"
" icon text');\nfprintf('','COMMENT: end icon text');\n"
sg_blockgui_xml "<!-- * Copyright (c) 2005, Xilinx, Inc. "
"All Rights Reserved. --><!-- * Reproduction or reuse, in any for"
"m, without the explicit written --><!-- * consent of Xilinx, Inc., is stri"
"ctly prohibited. --><sysgenblock has_userdata=\"true\" tag="
"\"genX\" block_type=\"sysgen\" simulinkname=\" System Generator\" >\n <icon w"
"idth=\"51\" bg_color=\"beige\" height=\"50\" caption_format=\"System\\nGenera"
"tor\" wmark_color=\"red\" />\n <callbacks DeleteFcn=\"xlSysgenGUI('delete', g"
"cs, gcbh);\" OpenFcn=\"xlSysgenGUI('startup',gcs,gcbh)\" ModelCloseFcn=\"xlSy"
"sgenGUI('Close',gcs,gcbh)\" PostSaveFcn=\"xlSysgenGUI('Save')\" />\n <librari"
"es>\n <library name=\"xbsIndex\" />\n <library name=\"xbsBasic\" />\n <lib"
"rary name=\"xbsTools\" />\n </libraries>\n <subsystem_model file=\"system_gen"
"erator_subsystem.mdl\" />\n <blockgui label=\"Xilinx System Generator\" >\n "
"<editbox evaluate=\"false\" multi_line=\"true\" name=\"infoedit\" read_only="
"\"true\" default=\" System Generator\" />\n <editbox evaluate=\"false\" name"
"=\"xilinxfamily\" default=\"Virtex4\" label=\"Xilinx family\" />\n <editbox "
"evaluate=\"false\" name=\"part\" default=\"xc4vsx35\" label=\"Part\" />\n <e"
"ditbox evaluate=\"false\" name=\"speed\" default=\"-10\" label=\"Speed\" />\n"
" <editbox evaluate=\"false\" name=\"package\" default=\"ff668\" label=\"Pack"
"age\" />\n <listbox evaluate=\"true\" name=\"synthesis_tool\" default=\"XST"
"\" label=\"Synthesis tool\" >\n <item value=\"Spectrum\" />\n <item value"
"=\"Synplify\" />\n <item value=\"Synplify Pro\" />\n <item value=\"XST\" "
"/>\n <item value=\"Precision\" />\n </listbox>\n <editbox evaluate=\"fals"
"e\" name=\"directory\" default=\"./netlist\" label=\"Target directory\" />\n "
" <checkbox evaluate=\"true\" name=\"testbench\" default=\"off\" label=\"Testb"
"ench\" />\n <editbox evaluate=\"true\" name=\"simulink_period\" default=\"1"
"\" label=\"Simulink period\" />\n <editbox evaluate=\"true\" name=\"sysclk_p"
"eriod\" default=\"10\" label=\"System clock period\" />\n <checkbox evaluate"
"=\"true\" name=\"incr_netlist\" default=\"off\" label=\"Incremental netlistin"
"g\" />\n <listbox evaluate=\"true\" name=\"trim_vbits\" default=\"Everywhere"
" in SubSystem\" label=\"Trim valid bits\" >\n <item value=\"According to Bl"
"ock Masks\" />\n <item value=\"Everywhere in SubSystem\" />\n <item value"
"=\"No Where in SubSystem\" />\n </listbox>\n <listbox evaluate=\"true\" nam"
"e=\"dbl_ovrd\" default=\"According to Block Masks\" label=\"Override with dou"
"bles\" >\n <item value=\"According to Block Masks\" />\n <item value=\"Ev"
"erywhere in SubSystem\" />\n <item value=\"No Where in SubSystem\" />\n </"
"listbox>\n <listbox evaluate=\"true\" name=\"core_generation\" default=\"Acc"
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