sdram_coreb.mak

blackfin的MDMA程序

# Generated by the VisualDSP++ IDDE

# Note:  Any changes made to this Makefile will be lost the next time the
# matching project file is loaded into the IDDE.  If you wish to preserve
# changes, rename this file and run it externally to the IDDE.

# The syntax of this Makefile is such that GNU Make v3.77 or higher is
# required.

# The current working directory should be the directory in which this
# Makefile resides.

# Supported targets:
#     SDRAM_CoreB_Debug
#     SDRAM_CoreB_Debug_clean

# Define this variable if you wish to run this Makefile on a host
# other than the host that created it and VisualDSP++ may be installed
# in a different directory.

ADI_DSP=C:\Program Files\Analog Devices\VisualDSP 5.0


# $VDSP is a gmake-friendly version of ADI_DIR

empty:=
space:= $(empty) $(empty)
VDSP_INTERMEDIATE=$(subst \,/,$(ADI_DSP))
VDSP=$(subst $(space),\$(space),$(VDSP_INTERMEDIATE))

RM=cmd /C del /F /Q

#
# Begin "SDRAM_CoreB_Debug" configuration
#

ifeq ($(MAKECMDGOALS),SDRAM_CoreB_Debug)

SDRAM_CoreB_Debug : ./Debug/SDRAM_CoreB.dxe 

Debug/Init_DMA.doj :Init_DMA.c main.h system.h $(VDSP)/Blackfin/include/cdefBF561.h $(VDSP)/Blackfin/include/defBF561.h $(VDSP)/Blackfin/include/def_LPBlackfin.h $(VDSP)/Blackfin/include/cdef_LPBlackfin.h $(VDSP)/Blackfin/include/ccblkfn.h $(VDSP)/Blackfin/include/stdlib.h $(VDSP)/Blackfin/include/yvals.h $(VDSP)/Blackfin/include/stdlib_bf.h $(VDSP)/Blackfin/include/builtins.h $(VDSP)/Blackfin/include/sys/builtins_support.h $(VDSP)/Blackfin/include/fract_typedef.h $(VDSP)/Blackfin/include/fr2x16_typedef.h $(VDSP)/Blackfin/include/r2x16_typedef.h $(VDSP)/Blackfin/include/raw_typedef.h $(VDSP)/Blackfin/include/sys/mc_typedef.h $(VDSP)/Blackfin/include/sys/exception.h 
	@echo ".\Init_DMA.c"
	$(VDSP)/ccblkfn.exe -c .\Init_DMA.c -file-attr ProjectName=SDRAM_CoreB -g -structs-do-not-overlap -no-multiline -D COREB -double-size-32 -decls-strong -multicore -warn-protos -si-revision 0.5 -proc ADSP-BF561 -o .\Debug\Init_DMA.doj -MM

Debug/Init_PLL_B.doj :Init_PLL_B.c main.h system.h $(VDSP)/Blackfin/include/cdefBF561.h $(VDSP)/Blackfin/include/defBF561.h $(VDSP)/Blackfin/include/def_LPBlackfin.h $(VDSP)/Blackfin/include/cdef_LPBlackfin.h $(VDSP)/Blackfin/include/ccblkfn.h $(VDSP)/Blackfin/include/stdlib.h $(VDSP)/Blackfin/include/yvals.h $(VDSP)/Blackfin/include/stdlib_bf.h $(VDSP)/Blackfin/include/builtins.h $(VDSP)/Blackfin/include/sys/builtins_support.h $(VDSP)/Blackfin/include/fract_typedef.h $(VDSP)/Blackfin/include/fr2x16_typedef.h $(VDSP)/Blackfin/include/r2x16_typedef.h $(VDSP)/Blackfin/include/raw_typedef.h $(VDSP)/Blackfin/include/sys/mc_typedef.h $(VDSP)/Blackfin/include/sys/exception.h 
	@echo ".\Init_PLL_B.c"
	$(VDSP)/ccblkfn.exe -c .\Init_PLL_B.c -file-attr ProjectName=SDRAM_CoreB -g -structs-do-not-overlap -no-multiline -D COREB -double-size-32 -decls-strong -multicore -warn-protos -si-revision 0.5 -proc ADSP-BF561 -o .\Debug\Init_PLL_B.doj -MM

Debug/Init_SD_RAM.doj :Init_SD_RAM.c main.h system.h $(VDSP)/Blackfin/include/cdefBF561.h $(VDSP)/Blackfin/include/defBF561.h $(VDSP)/Blackfin/include/def_LPBlackfin.h $(VDSP)/Blackfin/include/cdef_LPBlackfin.h $(VDSP)/Blackfin/include/ccblkfn.h $(VDSP)/Blackfin/include/stdlib.h $(VDSP)/Blackfin/include/yvals.h $(VDSP)/Blackfin/include/stdlib_bf.h $(VDSP)/Blackfin/include/builtins.h $(VDSP)/Blackfin/include/sys/builtins_support.h $(VDSP)/Blackfin/include/fract_typedef.h $(VDSP)/Blackfin/include/fr2x16_typedef.h $(VDSP)/Blackfin/include/r2x16_typedef.h $(VDSP)/Blackfin/include/raw_typedef.h $(VDSP)/Blackfin/include/sys/mc_typedef.h $(VDSP)/Blackfin/include/sys/exception.h 
	@echo ".\Init_SD_RAM.c"
	$(VDSP)/ccblkfn.exe -c .\Init_SD_RAM.c -file-attr ProjectName=SDRAM_CoreB -g -structs-do-not-overlap -no-multiline -D COREB -double-size-32 -decls-strong -multicore -warn-protos -si-revision 0.5 -proc ADSP-BF561 -o .\Debug\Init_SD_RAM.doj -MM

Debug/SDRAM_CoreB.doj :SDRAM_CoreB.c $(VDSP)/Blackfin/include/ccblkfn.h $(VDSP)/Blackfin/include/stdlib.h $(VDSP)/Blackfin/include/yvals.h $(VDSP)/Blackfin/include/stdlib_bf.h $(VDSP)/Blackfin/include/builtins.h $(VDSP)/Blackfin/include/sys/builtins_support.h $(VDSP)/Blackfin/include/fract_typedef.h $(VDSP)/Blackfin/include/fr2x16_typedef.h $(VDSP)/Blackfin/include/r2x16_typedef.h $(VDSP)/Blackfin/include/raw_typedef.h $(VDSP)/Blackfin/include/sys/mc_typedef.h $(VDSP)/Blackfin/include/cdefBF561.h $(VDSP)/Blackfin/include/defBF561.h $(VDSP)/Blackfin/include/def_LPBlackfin.h $(VDSP)/Blackfin/include/cdef_LPBlackfin.h main.h system.h $(VDSP)/Blackfin/include/sys/exception.h 
	@echo ".\SDRAM_CoreB.c"
	$(VDSP)/ccblkfn.exe -c .\SDRAM_CoreB.c -file-attr ProjectName=SDRAM_CoreB -g -structs-do-not-overlap -no-multiline -D COREB -double-size-32 -decls-strong -multicore -warn-protos -si-revision 0.5 -proc ADSP-BF561 -o .\Debug\SDRAM_CoreB.doj -MM

./Debug/SDRAM_CoreB.dxe :$(VDSP)/Blackfin/include/services/services_shared_symbols.h $(VDSP)/Blackfin/include/shared_symbols.h $(VDSP)/Blackfin/ldf/adsp-BF561.ldf ./local_shared_symbols.h $(VDSP)/Blackfin/lib/bf561_rev_0.5/crtsf561y.doj ./Debug/Init_DMA.doj ./Debug/Init_PLL_B.doj ./Debug/Init_SD_RAM.doj ./Debug/SDRAM_CoreB.doj $(VDSP)/Blackfin/lib/cplbtab561b.doj $(VDSP)/Blackfin/lib/bf561_rev_0.5/crtn561y.doj $(VDSP)/Blackfin/lib/bf561_rev_0.5/libmc561y.dlb $(VDSP)/Blackfin/lib/bf561_rev_0.5/libsmall561mty.dlb $(VDSP)/Blackfin/lib/bf561_rev_0.5/libio561mty.dlb $(VDSP)/Blackfin/lib/bf561_rev_0.5/libc561mty.dlb $(VDSP)/Blackfin/lib/bf561_rev_0.5/librt_fileio561mty.dlb $(VDSP)/Blackfin/lib/bf561_rev_0.5/libevent561mty.dlb $(VDSP)/Blackfin/lib/bf561_rev_0.5/libcpp561mty.dlb $(VDSP)/Blackfin/lib/bf561_rev_0.5/libcpprt561mty.dlb $(VDSP)/Blackfin/lib/bf561_rev_0.5/libx561mty.dlb $(VDSP)/Blackfin/lib/bf561_rev_0.5/libf64ieee561y.dlb $(VDSP)/Blackfin/lib/bf561_rev_0.5/libdsp561y.dlb $(VDSP)/Blackfin/lib/bf561_rev_0.5/libsftflt561y.dlb $(VDSP)/Blackfin/lib/bf561_rev_0.5/libetsi561y.dlb $(VDSP)/Blackfin/lib/bf561_rev_0.5/Debug/libssl561y.dlb $(VDSP)/Blackfin/lib/bf561_rev_0.5/Debug/libdrv561y.dlb $(VDSP)/Blackfin/lib/bf561_rev_0.5/Debug/libusb561y.dlb 
	@echo "Linking..."
	$(VDSP)/ccblkfn.exe .\Debug\Init_DMA.doj .\Debug\Init_PLL_B.doj .\Debug\Init_SD_RAM.doj .\Debug\SDRAM_CoreB.doj -L .\Debug -flags-link -MDCOREB,-MDOTHERCORE,-MDDEBUG -add-debug-libpaths -multicore -flags-link -MDUSE_SDRAM -flags-link -od,.\Debug -o .\Debug\SDRAM_CoreB.dxe -proc ADSP-BF561 -si-revision 0.5 -MM

endif

ifeq ($(MAKECMDGOALS),SDRAM_CoreB_Debug_clean)

SDRAM_CoreB_Debug_clean:
	-$(RM) "Debug\Init_DMA.doj"
	-$(RM) "Debug\Init_PLL_B.doj"
	-$(RM) "Debug\Init_SD_RAM.doj"
	-$(RM) "Debug\SDRAM_CoreB.doj"
	-$(RM) ".\Debug\SDRAM_CoreB.dxe"
	-$(RM) ".\Debug\*.ipa"
	-$(RM) ".\Debug\*.opa"
	-$(RM) ".\Debug\*.ti"
	-$(RM) ".\Debug\*.pgi"
	-$(RM) ".\*.rbld"

endif