📄 sub.med
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982 w2_to_sell:
983 ld ix,W2
984 ld iy,SELL
985 j move_9byte
986 w2_to_marg:
987 ld ix,W2
988 ld iy,MARG
989 j move_9byte
990 dt_to_prn:
991 ;V4.03 ld ix,DT_BUF
992 ;V4.03 ld iy,PRN_BUF
993 ;V4.03 j move_9byte
994 prn_to_dt:
995 ;V4.03 ld ix,PRN_BUF
996 ;V4.03 ld iy,DT_BUF
997 ;V4.03 j move_9byte
998
999 w1_to_w4:
1000 ld ix,W1
1001 ld iy,W4
1002 jp move_9byte
1003 w1_to_ftemp:
1004 ;V4.11 ld ix,W1
1005 ;V4.11 ld iy,FN_TEMP
1006 ;V4.11 jp move_9byte
1007 ftemp_to_w2:
1008 ;V4.11 ld ix,FN_TEMP
1009 ;V4.11 ld iy,W2
1010 ;V4.11 jp move_9byte
1011 w4_to_w1:
1012 ld ix,W4
1013 ld iy,W1
1014 jp move_9byte
1015 w2_to_w4:
1016 ld ix,W2
1017 ld iy,W4
1018 jp move_9byte
1019 w4_to_w2:
1020 ld ix,W4
1021 ld iy,W2
1022 jp move_9byte
1023
1024 move_9byte:
1025 ld c,9-1 ;move 9bytes
1026 move_nb0:
1027 ld a,(ix)
1028 ld (iy),a
1029 inc ix
1030 inc iy
1031 dec c
1032 j f,move_nb0 ;reg.c is not 0xff? yes->
1033 ret
1034 ;---------------------------------------
1035 w1_round:
1036 ld hl,W1
1037 jp wreg_round
1038 ;------------------------------
1039 w2_round:
1040 ld hl,W2
1041 ;------------------------------
1042 wreg_round:
1043 call wk_round
1044 ret
1045 ;------------------------------
1046 w1_round_print:
1047 call w1_round
1048 w1_print:
1049 ld hl,W1
1050 jp wreg_print
1051 ;------------------------------
1052 w2_round_print:
1053 call w2_round
1054 w2_print:
1055 ld hl,W2
1056 ;------------------------------
1057 ;==============================
1058 wreg_print:
1059 call wk_print
1060 ret
1061 ;==============================================================================
1062 ; Exchange work register use register: ix, iy, c, a, b
1063 ;==============================================================================
1064 exchg_w12:
1065 ld ix,W1
1066 ld iy,W2
1067 j exchg_9byte
1068 exchg_9byte:
1069 ld c,9-1 ;move 9bytes
1070 exchg_nb0:
1071 ld a,(ix)
1072 ld b,(iy)
1073 ld (ix),b
1074 ld (iy),a
1075 inc ix
1076 inc iy
1077 dec c
1078 j f,exchg_nb0 ;reg.c is not 0xff? yes->
1079 ret
1080
1081 ;==============================================================================
1082 ; ADD mode
1083 ;==============================================================================
1084 ;W2 shift to right(shift DP_POS times)
1085 ;ignore when not enter tenkey
1086 ;ignore when enter tenkey with DP
1087 add_mode:
1089 +1 ld wa,SW_A
1090 +1 test (SW_A>>4).a ;bit -reverse-> jump status
1091 +1 j f,add_mode_start ;if jump status is 0 -> branch
1093 +1 ld wa,SW_ADM
1094 +1 test (SW_ADM>>4).a ;bit -reverse-> jump status
1095 +1 j t,add_mode9 ;if jump status is 1 -> branch
1096 add_mode_start: ;V1.24
1098 +1 ld wa,F_TNKEY
1099 +1 test (F_TNKEY>>4).a ;bit -reverse-> jump status
1100 +1 j t,add_mode9 ;if jump status is 1 -> branch
1101 ;V1.33 ld a,(TEN_CT)
1102 ;V1.33 j z,add_mode9 ;if no tenkey entry yes -> ignore add mode
1104 +1 ld wa,F_DPIN
1105 +1 test (F_DPIN>>4).a ;bit -reverse-> jump status
1106 +1 j f,add_mode9 ;if jump status is 0 -> branch
1107 ld b,(DP_POS)
1108 j z,add_mode9
1109 call ten_to_w2 ;
1110 ;V3.04 call w2_zerock ;
1111 ;V3.04 j nz,add_mode3 ;V
1112 ;V3.04 and (W2_S),0x00 ;clear tenkey sign(not allowed -0 entry)
1113 add_mode3: ;
1114 ld a,(W2_DP) ;
1115 add a,(DP_POS) ;
1116 ld (W2_DP),a ;
1117 set cf ;C=1 means add mode shift
1118 ret ;
1119 add_mode9:
1120 clr cf ;C=0 means not add mode
1121 ret
1122
1123 ;==============================================================================
1124 ; DP adjustment(follow DP selector setting)
1125 ;==============================================================================
1126 ;transfer TENKEY to W2 with DP adjustment..............
1127 ten_to_w1dp:
1128 call ten_to_w1 ;V1.17
1129 ld hl,W1 ;V1.17
1130 call dp_adjust ;V1.17
1131 ret ;V1.17
1132 ten_to_w2dp:
1133 call ten_to_w2
1134 ;V3.04 call w2_zerock;V1.13 V1.36
1135 ;V3.04 j nz,ten_to_w2dp5;V1.13 V1.36
1136 ;V3.04 and (W2_S),0x00;V1.13 V1.36 ;clear tenkey sign(not allowed -0 entry)
1137 ten_to_w2dp5:
1138 ld hl,W2
1139 call dp_adjust
1140 ret
1141
1142 ;DP location is adjusted by follow DP selector value...............
1143 ;input: HL <- work resister top address(keep hl content)
1144 ; DP_POS <- DP selector value (0,1,2,3,4,6)
1145 dp_adjust:
1146 ld a,(hl+OFF_DP) ;
1147 cmp a,(DP_POS) ;compare work register DP <> DP selector value
1148 j lt,dp_adj_00 ;lower than DP selector -> work reg. left shift(add 0 to under DP)
1149 j gt,dp_adj_10 ;greater than DP selector -> work reg. right shift(remove 0 from under DP)
1150 dp_adj_90:
1151 ret
1152
1153 ;work reg. left shift....................
1154 dp_adj_00:
1155 ;V1.21 @if(@eqs(@D14,@ON))then(
1156 ;V1.21 ld a,(hl+OFF_MSD) ;check MSD (in case of 14digit)
1157 ;V1.21 )else (
1158 ;V1.21 ld a,(hl+OFF_MSD12) ;check MSD (in case of 12digit)
1159 ;V1.21 )fi
1161 +1 ld wa,M14
1162 +1 test (M14>>4).a ;bit -reverse-> jump status
1163 +1 j t,dp_adj_0x ;if jump status is 1 -> branch
1164 ld a,(hl+OFF_MSD) ;V1.21check MSD (in case of 14digit)
1165 jp dp_adj_0z ;V1.21
1166 dp_adj_0x: ;V1.21
1168 +1 ld wa,M10
1169 +1 test (M10>>4).a ;bit -reverse-> jump status
1170 +1 j f,dp_adj_0y ;if jump status is 0 -> branch
1171 ld a,(hl+OFF_MSD12) ;V1.21check MSD (in case of 12digit)
1172 jp dp_adj_0z ;V1.21
1173 dp_adj_0y: ;V1.21
1174 ld a,(hl+OFF_MSD10) ;v1.21
1175 dp_adj_0z: ;V1.21
1177 +1 test (FINANCE_1).3
1178 j t,dp_adj_01 ;V1.07
1179 ld a,(hl+OFF_MSD) ;V1.07
1180 dp_adj_01: ;V1.07
1181 and a,0xf0
1182 j nz,dp_adj_90 ;found data at MSD yes-> exit
1183 call stg_sfl47 ;work reg. left shift by nibble
1184 inc (hl+OFF_DP) ;DP+1
1185 j dp_adjust
1186
1187 ;work reg. right shift....................
1188 dp_adj_10:
1189 ld a,(hl+OFF_LSD) ;check LSD
1190 and a,0x0f
1191 j nz,dp_adj_90 ;found data at LSD yes-> exit
1192 call stg_sfr47 ;work reg. right shift by nibble
1193 dec (hl+OFF_DP) ;DP-1
1194 j dp_adjust
1195 ;==============================================================================
1196 ;V2.10-----------------------------------
1197 wk_round_down:
1198 ld a,(MDFLG_1)
1199 push a
1201 +1 ld wa,SW_RND54
1202 +1 clr (SW_RND54>>4).a
1204 +1 ld wa,SW_RNDUP
1205 +1 clr (SW_RNDUP>>4).a
1206 call wk_round
1207 pop a
1208 ld (MDFLG_1),a
1209 ret
1210
1211 wk_round_up:
1212 ld a,(MDFLG_1)
1213 push a
1215 +1 ld wa,SW_RND54
1216 +1 clr (SW_RND54>>4).a
1218 +1 ld wa,SW_RNDUP
1219 +1 set (SW_RNDUP>>4).a
1220 call wk_round
1221 pop a
1222 ld (MDFLG_1),a
1223 ret
1224 ;================================================
1225 wk_round_with_2DP:
1226 ld a,(DP_POS)
1227 push a
1228 ld a,2
1229 ld (DP_POS),a
1230 jp wk_round_with_ten_dp_1
1231 ;--------------------------------
1232 wk_round_with_const_dp:
1233 ld a,(DP_POS)
1234 push a
1235 ld a,(CONST+OFF_DP)
1236 jp wk_round_with_ten_dp_0
1237 ;-------------------------------
1238 wk_round_with_ten_dp:
1239 ld a,(DP_POS)
1240 push a
1241 ld a,(TEN_DP)
1242 ;--------------------------------
1243 wk_round_with_ten_dp_0:
1244 cmp a,(DP_POS)
1245 j le,wk_round_with_ten_dp_1
1246 ld (DP_POS),a
1247 wk_round_with_ten_dp_1:
1248 ;V1.31 call wk_round_0
1249 call wk_round ;V1.31
1250 pop a
1251 ld (DP_POS),a
1252 ret
1253 ;==============================================================================
1254 ; work resister rounding
1255 ;==============================================================================
1256 ;work registor rounding follow DP_POS and RND_STS
1257 ; input: hl <- work reg. address (keep hl content)
1258 ; DP_POS <- DP selector value (0,1,2,3,4,6)
1259 ; MDFLG_0 <- DP selector position(if no any flag turn on means 'FDP')
1260 ; SW_RNDUP,SW_RND54 (rounding selector status)
1261 wk_round:
1262 ld a,(MDFLG_0) ;if selected floting DP
1263 j nz,wk_round_0 ; no -> rounding process
1264 wkrnd_zsp0: ;
1265 ld a,(hl+OFF_DP) ;
1266 j z,wkrnd_zsp9 ;DP is zero? yes -> exit
1267 ld a,(hl+OFF_LSD) ;check LSD
1268 and a,0x0f ;
1269 j nz,wkrnd_zsp9 ;having data on last digit? yes-> stop right shift
1270 call stg_sfr47 ;work reg. right shift by nibble
1271 dec (hl+OFF_DP) ;DP-1
1272 j wkrnd_zsp0 ;
1273 wkrnd_zsp9: ;
1274 j wk_round_9 ;-> exit
1275 wk_round_0: ;
1276
1277 ld a,(hl+OFF_DP) ;
1278 cmp a,(DP_POS) ;compare work register DP <> DP selector value
1279 j lt,dp_adj_00 ;lower than DP selector -> jump to dp_adjust routine(left shift)
1280 j gt,wk_rnd_10 ;greater than DP selector -> work reg. right shift
1281 wk_round_9:
1282 ;V1.28 @BBS (M_V1297,wk_round_99) ;V1.26
1283 ;V1.28 @BBC (M_V1205,wk_round_99) ;V1.28
1284 ;V3.04 call _zerock ;V1.28 ;zero check working register(hl)V1.36
1285 ;V3.04 j nz,wk_round_99 ;V1.28 V1.36
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