📄 eeprom.med
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951 ;=====================================================
952 ee_write: ;the data in register b(high 8bit)c(low 8bit)-->EEPROM
953 ; xxxxxxxx xxxxxxxx
955 +1 set (FLG_2).4
956 ld w,3
957 ee_write_x:
958 push w ;V1.05
960 +1 set (P0CR).EP_DIO ;as output port
961 +1 clr (P0DR).EP_DIO ;
962 nop ;V1.34
963 nop ;V1.34
964 nop ;V1.34
965 nop ;V1.34
966 ld de,bc ;backup bc in de
968 +1 set (P0DR).EP_CS
969 nop
970 nop
971 nop
972 nop
973 nop
974 call high_out ;start bit is high level
975 ld a,(EP_ADDR) ;EPROM address-->a
976 and a,0y00111111 ;EEPROM address only from 00-->63
977 or a,0y01000000 ;write instruction is 01xxxxxx
978 call data_out ;instruction for write and address send to EEPROM
979 ld a,b ;the data in c-->a
980 call data_out ;a-->EEPROM
981 ld a,c ;the data in b-->a
982 call data_out ;a-->EEPROM
984 +1 clr (P0DR).EP_DIO
985 call ee_wait_10_nop ;V1.34
986 nop ;V1.34
987 nop ;V1.34
988 nop ;V1.34
990 +1 clr (P0DR).EP_CS
991 call ee_wait_10_nop ;V1.34
993 +1 clr (P0CR).EP_DIO ;P17 as inupt port
994 +1 set (P0DR).EP_DIO
995 call ee_wait_10_nop ;V1.34
997 +1 set (P0DR).EP_CS
998 call ee_wait_10_nop ;V1.34
999 ld (EP_TIM),EETIM ;set time for waiting STOP signal. dec EP_TIM in timer interrupt
1000 ee_write0:
1002 +1 clr (P0CR).EP_DIO ;P17 as inupt port
1003 +1 set (P0DR).EP_DIO
1004 nop
1005 test (P0DR).EP_DIO
1006 j f,ee_write1 ;STOP flag received? yes-->
1007 ld a,(EP_TIM) ;not receive STOP flag
1008 j ne,ee_write0
1010 +1 ld wa,EP_FAIL
1011 +1 set (EP_FAIL>>4).a
1013 +1 clr (P0DR).EP_CS
1015 +1 set (P0CR).EP_DIO ;as output port
1016 +1 clr (P0DR).EP_DIO ;
1018 +1 clr (FLG_2).4
1019 pop w ;V1.05
1020 ret
1021 ee_write1: ;
1023 +1 clr (P0DR).EP_CS
1024 call ee_wait_10_nop ;V1.34
1025 call ee_read ;16bit data read into bc
1026 pop w ;V1.05
1027 cmp bc,de ;the data read (bc) is same as write (de)
1028 j eq,ee_write9
1029 ee_write5:
1030 dec w ; if compare the data is different,double sure by retry write--read 3 times
1031 j eq,ee_write8 ;
1032 ld bc,de ;resume de to bc
1033 jp ee_write_x ;
1034 ee_write8:
1036 +1 ld wa,EP_FAIL
1037 +1 set (EP_FAIL>>4).a
1038 ee_write9:
1040 +1 clr (FLG_2).4
1041 ret
1042 ;===========================================================
1043
1044 ;===========================================================
1045 ee_read:
1047 +1 set (FLG_2).4
1048 ld (EP_TIM),EETIM
1049 ee_read_0:
1051 +1 set (P0CR).EP_DIO ;as output port
1052 +1 clr (P0DR).EP_DIO ;
1053 nop ;V1.34
1054 nop ;V1.34
1055 nop ;V1.34
1057 +1 set (P0DR).EP_CS
1058 call ee_wait_10_nop ;V1.34
1059 call high_out ;start bit output
1060 ld a,(EP_ADDR) ;
1061 and a,0y00111111 ;address from 0~63
1062 or a,0y10000000 ;instruction read from EEPROM: 10xxxxxx
1063 call data_out ;output read instruction and address
1065 +1 clr (P0DR).EP_DIO
1066 nop ;V1.34
1067 nop ;V1.34
1068 nop ;V1.34
1070 +1 clr (P0CR).EP_DIO ;P17 as inupt port
1071 +1 set (P0DR).EP_DIO
1072 call data_in ;16bit data readed from EEEPROM and save in b,c
1073 ld b,a ;D8~D15 saved in regiser c
1074 call data_in
1075 ld c,a ;D0~D7 saved inregister b
1077 +1 clr (P0DR).EP_CS
1078 call ee_wait_10_nop ;V1.34
1079 ;read one time again
1081 +1 set (P0CR).EP_DIO ;as output port
1082 +1 clr (P0DR).EP_DIO ;
1083 nop ;V1.34
1084 nop ;V1.34
1085 nop ;V1.34
1087 +1 set (P0DR).EP_CS
1088 call ee_wait_10_nop ;V1.34
1089 call high_out
1090 ld a,(EP_ADDR)
1091 and a,0y00111111
1092 or a,0y10000000
1093 call data_out
1095 +1 clr (P0DR).EP_DIO
1096 nop ;V1.34
1097 nop ;v1.34
1098 nop ;V1.34
1100 +1 clr (P0CR).EP_DIO ;P17 as inupt port
1101 +1 set (P0DR).EP_DIO
1102 call data_in
1103 ld d,a ;D8~D15
1104 call data_in
1105 ld e,a ;D0~D7
1106 cmp de,bc
1107 j ne,ee_read_err
1109 +1 clr (P0DR).EP_CS
1110 nop ;V1.34
1111 nop ;V1.34
1112 nop ;v1.34
1114 +1 set (P0CR).EP_DIO ;as output port
1115 +1 clr (P0DR).EP_DIO ;
1117 +1 clr (FLG_2).4
1118 ret
1119 ee_read_err:
1121 +1 clr (P0DR).EP_CS
1122 ld a,(EP_TIM)
1123 j ne,ee_read_0
1125 +1 ld wa,EP_FAIL
1126 +1 set (EP_FAIL>>4).a
1128 +1 clr (FLG_2).4
1129 ret
1130
1131 ;===============================================================
1132 eeprom_check: ;read the data from EEPROM (00h) and (3fh), and compare with check_code
1133 ;
1134 ld (EP_ADDR),EE_TEST1 ;check the data in EEPROM register (0000h)
1135 call ee_read
1136 cmp bc,(check_code)
1137 j ne,eeprom_err
1138 ld (EP_ADDR),EE_TEST2 ;check the data in EEPROM register(003fh)
1139 call ee_read
1140 cmp bc,(check_code)
1141 j ne,eeprom_err
1142 clr cf ;clear cf indicate EEPROM check succeed
1143 ret
1144 eeprom_err:
1145 set cf ;set cf indicate EEPROM check fail
1146 ret
1147
1148 ;====================================================================
1149 ee_to_euro1:
1150 ld hl,EURO_RATE1+OFF_MSD
1151 jp ee_to_euro
1152 ee_to_euro2:
1153 ld hl,EURO_RATE2+OFF_MSD
1154 ee_to_euro:
1155 ld w,RATE_L
1156 mul w,a
1157 clr cf
1158 add a,EE_EU1
1159 ld (EP_ADDR),a
1160
1161 jp ee_to_wkreg
1162 ee_to_tax:
1163 ld (EP_ADDR),EE_TAX
1164 ld hl,TAXRT+OFF_MSD
1165 jp ee_to_wkreg
1166
1167 ee_to_tax2:
1168 ld (EP_ADDR),EE_TAX2
1169 ld hl,TAX2RT+OFF_MSD
1170 jp ee_to_wkreg
1171 ee_to_ten: ;
1172 ld w,RATE_L ;
1173 mul w,a ;
1174 clr cf ;
1175 add a,EE_EU1 ;
1176 ld (EP_ADDR),a ;
1177 call ten_clear
1178 ld hl,TENKEY+1 ;TEN_MSD
1179 ;====================================================================
1180 ;read 8bytes data from EEPROM-->(hl)-->work register buffer
1181 ;====================================================================
1182 ee_to_wkreg:
1184 +1 ld wa,EP_FAIL
1185 +1 test (EP_FAIL>>4).a ;bit -reverse-> jump status
1186 +1 j t,ee_to_wkreg_ok ;if jump status is 1 -> branch
1187 ret
1188 ee_to_wkreg_ok:
1189 ld d,0
1190 ld e,RATE_L ;4 word read
1191 ee_to_wkreg0:
1192 push de ;backup de register
1193 call ee_read ;EPROM-->bc
1194 pop de ;popout de register
1195 ld wa,bc ;backup bc
1196 ld c,d ;pointer for wk buffer-->c
1197 ld (hl+c),w ;\
1198 inc d ;|wa-->wk buffer
1199 inc c
1200 ld (hl+c),a ;|increase d point to next buffer
1201 inc d ;/
1202 inc (EP_ADDR)
1203 dec e
1204 j ne,ee_to_wkreg0 ;finished 8byte read and save into buffer
1205 ;------------adjust wk bufer data is available? digit not over 9, decimal not over 14
1206 ld c,0
1207 ee_to_wreg1:
1208 ld a,(hl+c)
1209 ld w,a ;backup a into w
1210 and a,0xf0
1211 cmp a,0xa0
1212 j lt,ee_to_wreg1_1
1213 and w,0x0f ;up nibble cleared to "0"
1214 ee_to_wreg1_1:
1215 ld a,w
1216 and a,0x0f
1217 cmp a,0x0a
1218 j lt,ee_to_wreg1_2
1219 and w,0x0f
1220 ee_to_wreg1_2:
1221 ld (hl+c),w ;update(return) w to wk buffer.
1222 inc c
1223 cmp c,OFF_DP
1224 j lt,ee_to_wreg1
1225 ;--------adjust the exp, can not over 15. e.g. 0.123456789012
1226 ld a,(hl+c)
1227 cmp a,14 ;exp over 14?
1228 j lt,ee_to_wreg2
1229 ld (hl+c),0
1230 ee_to_wreg2:
1231 ret
1232 ;==============================================================================
1233 w2_to_eetx2:
1234 ld (EP_ADDR),EE_TAX2
1235 ld hl,W2_MSD ;the first work buffer address
1236 jp wkreg_to_ee
1237 w2_to_eetx:
1238 ld (EP_ADDR),EE_TAX
1239 ld hl,W2_MSD ;the first work buffer address
1240 jp wkreg_to_ee
1241
1242 w2_to_ee:
1243 ld w,RATE_L
1244 mul w,a
1245 clr cf
1246 add a,EE_EU1
1247 ld (EP_ADDR),a
1248 ld hl,W2_MSD ;the first work buffer address
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