📄 eeprom.med
字号:
=1 632 ;V3.00S_CLR equ 0x07 ;'c '
=1 633 ;V3.00S_MTL equ 0x0e ;'M*'
=1 634 ;V3.00S_MST equ 0x0d ;'M<>'
=1 635 ;V3.00S_MPL equ 0x0b ;'M+'
=1 636 ;V3.00S_MMI equ 0x0c ;'M-'
=1 637 ;V3.00S_M2TL equ 0x10 ;'G*'
=1 638 ;V3.00S_STASTA equ 0x77 ;'**'
=1 639 ;V3.00S_M2ST equ 0x0f ;'G<>'
=1 640 ;V3.00S_STAS equ 0x76 ;'*S'
=1 641 ;V3.00S_M2PL equ 0x3e ;'G+'
=1 642 ;V3.00S_STAPL equ 0x73 ;'*+'
=1 643 ;V3.00S_PLSTA equ 0x37 ;'+*'
=1 644 ;V3.00S_M2MI equ 0x3f ;'G-'
=1 645 ;V3.00S_STAMN equ 0x70 ;'*-'
=1 646 ;V3.00S_M2TLV equ 0x97 ;'G*'
=1 647 ;V3.00S_M2STV equ 0x96 ;'G<>'
=1 648 ;V3.00S_M2PLV equ 0x3e ;'G+'
=1 649 ;V3.00S_M2MIV equ 0x3f ;'G-'
=1 650 ;V3.00S_PER equ 0x06 ;' %'
=1 651 ;V3.00S_STAPER equ 0x71 ;'*%'
=1 652 ;V3.00S_PRDS equ 0x01 ;'-%'
=1 653 ;V3.00S_PRAD equ 0x31 ;'+%'
=1 654 ;V3.00S_DLTAL equ 0x82 ;delta+' '
=1 655 ;V3.00S_DLTA equ 0x28 ;' "+delta V1.26
=1 656 ;V3.00S_PRDL equ 0x81 ;delta+'%'
=1 657 ;V3.00S_DLAS equ 0x87 ;delta+'*'
=1 658 ;V3.00S_PRMU equ 0x21 ;' %'
=1 659 ;V3.00S_MKUP equ 0xa2 ;'M '
=1 660 ;V3.00S_RVS equ 0x22 ;' '
=1 661 ;V3.00S_AVR equ 0x27 ;' *'
=1 662 ;V3.00S_ROOT equ 0x22 ;' '
=1 663 ;V3.00S_TAX equ 0x12 ;'% '
=1 664 ;V3.00S_PRN equ 0x62 ;'<> '
=1 665 ;V3.00S_EUR equ 0x22 ;' '
=1 666 ;V3.00S_EUEQ equ 0xc2 ;'= '
=1 667 ;V3.00S_COST equ 0x2b ;' C'
=1 668 ;V3.00S_SELL equ 0x26 ;' <>'
=1 669 ;V3.00S_M equ 0x2a ;' M'
=1 670 ;V3.00S_MARG equ 0xa1 ;'M%'
=1 671 ;V3.00S_PERMARG equ 0x1a ;'%M'
=1 672 ;V3.00S_TAXA equ 0x27 ;' *'
=1 673 ;V3.00S_ICG equ 0x29 ;' G'
=1 674 ;V3.00S_ICGV equ 0x29 ;' G'
=1 675 ;V3.00S_ICM equ 0x2a ;' M'
=1 676 ;V3.00S_ASM equ 0x7a ;'*M'
=1 677 ;V3.00S_ASC equ 0x7b ;'*C'
=1 678 ;V3.00S_ASDL equ 0x78 ;'*'+delta
=1 679 ;V3.00S_MIPL equ 0x03 ;'-+'
=1 680 ;V3.00S_MIMI equ 0x00 ;'--'
=1 681 ;V3.00S_MIST equ 0x06 ;'-S'
=1 682 ;V3.00S_MITL equ 0x07 ;'-T'
=1 683 ;V3.00S_EUROS equ 0x29 ;' euro'
=1 684 ;V3.00S_G equ 0x9f ;'G '
=1 685 ;V3.00S_GPL equ 0x93 ;'G+'
=1 686 ;V3.00S_GAST equ 0x97 ;'G*'
=1 687 ;==============================================================================
=1 688 P_SPC equ 0x20 ;for print " "
=1 689 ;-----------------------------------------------------------
=1 690 ;interrupt enable flag set:
=1 691
=1 692 EF4 equ 4;(EIRL).4 /INT0
=1 693 EF5 equ 5;(EIRL).5 INTTC1
=1 694 EF6 equ 6;(EIRL).6 INT1
=1 695 EF7 equ 7;(EIRL).7 INTTBT
=1 696 EF8 equ 0;(EIRH).0 INTTC3
=1 697 EF9 equ 1;(EIRH).1 INTSIO(High speed SIO interrupt)
=1 698 EF10 equ 2;(EIRH).2 INTTC4
=1 699 EF11 equ 3;(EIRH).3 INT3
=1 700 EF12 equ 4;(EIRH).4 INT4
=1 701 EF13 equ 5;(EIRH).5 INTTC2
=1 702 EF14 equ 6;(EIRH).6 /INT5
=1 703 EF15 equ 7;(EIRH).7 INTADC or INT2
=1 704 ;interrupt request flag set:
=1 705 IL2 equ 2;(ILL).2 INTSWI
=1 706 IL3 equ 3;(ILL).3 INTATRAP
=1 707 IL4 equ 4;(ILL).4 /INT0
=1 708 IL5 equ 5;(ILL).5 INTTC1
=1 709 IL6 equ 6;(ILL).6 INT1
=1 710 IL7 equ 7;(ILL).7 INTTB
=1 711 IL8 equ 0;(ILH).0 INTTC3
=1 712 IL9 equ 1;(ILH).1 INTSIO
=1 713 IL10 equ 2;(ILH).2 INTTC4
=1 714 IL11 equ 3;(ILH).3 INT3
=1 715 IL12 equ 4;(ILH).4 INT4
=1 716 IL13 equ 5;(ILH).5 INTTC2
=1 717 IL14 equ 6;(ILH).6 /INT5
=1 718 IL15 equ 7;(ILH).7 INTADC or /INT2
=1 719 ; DBR_LCD_RATE equ (0x0f33<<4)+5 ;LCD DBR matrix point for "RATE"
=1 720 ; DBR_LCD1235_RATE equ (0x0f33<<4)+3 ;LCD DBR matrix point for "RATE"
=1 721 ; DBR_LCD1297_RATE equ (0x0f33<<4)+4 ;LCD DBR matrix point for "RATE"
=1 722 ; DBR_LCD120_RATE equ (0x0f33<<4)+4 ;LCD DBR matrix point for "RATE"
=1 723 ; DBR_LCD1297_GT equ (0x0f32<<4)+2 ;LCD DBR matrix point for "GT"
=1 724 ; ;LCD_PRN equ (0x0f31<<4)+3 ;LCD DBR matrix point for "PRINT"
=1 725 ; ;LCD_FIN equ (0x0f30<<4)+3 ;LCD DEB matrix point for "FIN"
=1 726
=1 727 AUTOOFFTIME equ 31250;1500
728 public ee_to_euro1,ee_to_euro2,ee_to_tax,ee_to_ten,ee_to_wkreg,eeprom_check
729 public w2_to_ee,w2_to_eetx,w2_to_eetx2
730 public country_to_ee,ee_country_read,rate_init_check,ee_rate_init
731 public ee_to_tax2 ;V2.05,euro_country_set
732 public euro_fix_rate_tbl
733 extern init_keybuf,wait_100ms,key_get ;V2.04
734 $list
735 ;================================================
736 ;P0DR port
737 EP_CS equ 7 ;P07
738 EP_SK equ 6 ;P06
739 EP_DIO equ 5 ;P05
740
741 RATE_L equ 4 ;constant
742 EE_TEST1 equ 0x00
743 EE_COUNTRY equ 0x01 ;save country code
744 EE_EU1 equ 0x02
745 EE_EU2 equ EE_EU1+RATE_L
746 EE_EU3 equ EE_EU2+RATE_L
747 EE_EU4 equ EE_EU3+RATE_L
748 EE_EU5 equ EE_EU4+RATE_L
749 EE_EU6 equ EE_EU5+RATE_L
750 EE_EU7 equ EE_EU6+RATE_L
751 EE_EU8 equ EE_EU7+RATE_L
752 EE_EU9 equ EE_EU8+RATE_L
753 EE_EU10 equ EE_EU9+RATE_L
754 EE_EU11 equ EE_EU10+RATE_L
755 EE_EU12 equ EE_EU11+RATE_L
756 EE_EU13 equ EE_EU12+RATE_L
757 EE_TAX equ EE_EU13+RATE_L
758 EE_TAX2 equ EE_TAX+RATE_L
759 EE_TEST2 equ EE_TAX2+RATE_L
760 ;================================================
761 ROM section code
762 ;=========================================================================
767 ;-----------------------------------------------------------------
772 ;==========================================================================
776 ;-----------------------------
780 ;-----------------------------
784 ;-----------------------------
788 ;-----------------------------
792 ;-----------------------------
796 ;-----------------------------
800 ;-----------------------------
804 ;-----------------------------
805 EETIM equ 30 ;v1.20
806 ;========================================================================
807 ;EEPROM 93LC46 1024bit (128 Bytes)
808 ;request: Tcs > 250ns; Tsk < 1MHz; Tdio > 100ns
809 ;EEPROM instruction code
810 ;READ 10AAAAAA
811 ;Write Enable 0011xxxx
812 ;WRITE 01AAAAAA
813 ;Write All Register 0001xxxx
814 ;Write Disable 0000xxxx
815 ;ERASE 11AAAAAA
816 ;Erase All Register 0010xxxx
817 ;data flow:------------------------------------------
818 ;write: 16bit data in bc--->a--->EEPROM
819 ;read: 16bit data in EEPTROM--->a--->bc
820 ;used general register: w,a,bc,de
821 ;=========================================================================
822 ee_enable: ;instruction 0011xxxx send to EEPROM
824 +1 set (FLG_2).4
826 +1 set (P0CR).EP_DIO ;as output port
827 +1 clr (P0DR).EP_DIO ;
828 nop ;V1.34
829 nop ;V1.34
830 nop ;V1.34
832 +1 set (P0DR).EP_CS
833 call ee_wait_10_nop ;V1.34
834 call high_out ;outpu high level from port EP_DIO; start bit is high
835 ld a,0y00110000 ;instructin Write Enable
836 call data_out
838 +1 clr (P0DR).EP_CS
839 nop ;V1.34
840 nop ;V1.34
841 nop ;V1.34
843 +1 set (P0CR).EP_DIO ;as output port
844 +1 clr (P0DR).EP_DIO ;
845 nop
847 +1 clr (FLG_2).4
848 ret
849 ;=====================================================
850 ee_disable: ;instruction 0000xxxx send to EEPROM
852 +1 set (FLG_2).4
854 +1 set (P0CR).EP_DIO ;as output port
855 +1 clr (P0DR).EP_DIO ;
856 nop ;V1.34
857 nop ;V1.34
858 nop ;V1.34
860 +1 set (P0DR).EP_CS
861 call ee_wait_10_nop ;V1.34
862 call high_out
863 ld a,0y00000000
864 call data_out
866 +1 clr (P0DR).EP_CS
867 nop ;V1.34
868 nop ;V1.34
869 nop ;V1.34
870 nop ;V1.34
872 +1 set (P0CR).EP_DIO ;as output port
873 +1 clr (P0DR).EP_DIO ;
874 nop
876 +1 clr (FLG_2).4
877 ret
878 ;=====================================================
879 high_out: ;output high level from port EP_DIO
881 +1 set (P0DR).EP_DIO
882 call ee_wait_10_nop ;V1.34
884 +1 set (P0DR).EP_SK
885 call ee_wait_10_nop ;V1.34
886 nop ;SK _HHHHHH____
887 nop ;DIO ___HHH_____
889 +1 clr (P0DR).EP_SK
890 nop ;
891 nop
892 ret ;
893 ;=====================================================
894 low_out: ;output low level from port EP_DIO
896 +1 clr (P0DR).EP_DIO
897 call ee_wait_10_nop ;V1.34
898 nop ;CS HHHHHHHHHHH
899 nop ;SK _HHHHHH____
901 +1 set (P0DR).EP_SK
902 call ee_wait_10_nop ;V1.34
904 +1 clr (P0DR).EP_SK
905 nop ;
906 nop
907 ret ;
908 ;=====================================================
909 data_out: ;8bit data in register "a" sent to EEPROM bit by bit
910 ld w,7 ;
911 data_out0: ;
912 shlc a ;CS HHHHHHHHHHHHHHHHHHHHHHHH
913 j cc,data_out2 ;SK _HHH__HHH__HHH_//_HHH_
914 call high_out ;DO __XXXXXXXXXXXXX//XXXX__
915 jp data_out4 ;
916 data_out2: ;
917 call low_out ;
918 data_out4: ;
919 dec w ;
920 jr f,data_out0 ;
921 ret ;
922 ;=====================================================
923 data_in: ;read 8bit data from EEPRM and save into register "a" bit by bit
924 ld w,7 ;
925 data_in0: ;
927 +1 set (P0DR).EP_SK
928 nop
929 nop
930 nop
932 +1 clr (P0CR).EP_DIO ;P17 as inupt port
933 +1 set (P0DR).EP_DIO
934 call ee_wait_10_nop ;V1.34
935 test (P0DR).EP_DIO
936 j t,data_in1 ;judge the port EP_DIO is high or low.
937 set cf ;is high
938 jp data_in2 ;
939 data_in1: ;
940 clr cf ;is low
941 data_in2: ;
942 rolc a ;16bit data read into register wa
944 +1 clr (P0DR).EP_SK
945 call ee_wait_10_nop ;V1.34
946 nop ;SK _HHH__HHH__HHH_//_HHH_
947 nop ;DO __XXXXXXXXXXXXX//XXXX__-->C-->register a
948 dec w ;
949 jr f,data_in0 ;
950 ret ;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -