interval_tm.mac

calculator code ,use toshibaor nec LSI

	$nolist
;*******************************************************************************
;*******************************************************************************
;*                                                                             *
;*              (C)Copyright, CLOVER China Electronics Co.,LTD.                *
;*                         (Company No:190077-X)                               *
;*                          All Rigits Reserved                                *
;*   add:No.58-F Yang Dong Road, LuoFeng Demonstrative Zone Suzhou, China      *
;*                    Tel: [phone] Fax:[phone]                     *
;*                        http://www.clover.co.jp                              *
;*                                                                             *
;*******************************************************************************
;*******************************************************************************
;
;		OBS CPD3212T source program
;		CPU: TOSHIBA TLC-870/C series TMP86CM74AF
;		RAM: 2Kbytes(0040h - 083Fh)
;		ROM: 32Kbytes(8000h - FFFFh)
;
;
;Sub routines

	?trigger(@)
	@include	"symdef_ram.inc"
	@include	"symdef_sub.inc"
	@include	"macro.inc"
	@include	"define.inc"
	$list

	public	interval_tm,init_pf,wait_40c
	extern	lcd_disable,init_io,resume,rtc_intsub,rtc_1sto128,rtc_128to1s

ROM	section	code 

;I/O port bit assignment for reference........................ 
;------------------------------------------------
;Port assignment (P1DR)
;------------------------------------------------
;P10	Power failure detection in	(TC2)	;8bit input/Nch.O.D or CMOS output
;Bit assignment of SYSCR2
;
;	 7	 6	 5	 4	 3	 2	 1	 0
;	XEN	XTEN	SYSCK	IDLE	 -	TGHALT	 -	 -
;
;	XEN    0: stop main clock 	1: start main clock
;	XTEN   0: stop sub clock	1: start sub clock
;	SYSCK  0: select main clock	1: select sub clock
;	IDLE   0: CPU,EDT enable	1: CPU,WDT disable(IDLE1/IDLE2/SLEEP mode)
;	TGHALT 0: TG enable		1: TG disable(IDLE0/SLEEP0 mode)
;
;
PF_JUDGE	equ	3
;PF_JUDGE	equ	2

;==============================================================================
;	Interval timer & Power failure controle(Clock source is Main oscilator)
;==============================================================================
;Initialize TC3 for power failure detection............
init_pf:
		ld	(TC3SEL),0y00000000	;V1.18 select INTTC3
		ld	(TC3CR),0y00001010	;TC3S=0(count stop) TC3CK=101(select fc/2^8) TC3M=0(select 8bit timer mode)
		ld	(TC3DRA),244		;800000/244.14/256=128Hz
		clr	(ILH).IL8		;
		di			;V2.05
		set	(EIRH).EF8		;TC3 interrupt enable
		ei			;V2.05
		ld	(TC3CR),0y00011010	;T32S=1(count start)
		ret

;==============================================================================
;	TC3 interrupt (1/128sec Interval timer and Check PF port).............
;==============================================================================
interval_tm:
;V2.00		dec	(TC3_COUNT)		;V1.50
;V2.00		and	(TC3_COUNT),0y00000001	;V1.50
;V2.00		j	z,interval_tm_start	;V1.50
;V2.00		reti				;V1.50
;V2.00interval_tm_start:
		@PUSH_REG
		@BBS	(IO_MT,pf_det92)
		@BBS	(EP_ACCES,pf_det92)
		call	rtc_intsub			;for interrupt sub routine for RTC(down count timer and display brink)

pf_detect:
		@BBC	(IO_PF,pf_det90)		;power failure?  no->
		@BBS	(F_WAITP,pf_det92)		;V1.30	only for no real time mode
		inc	(PF_CNT)
		cmp	(PF_CNT),PF_JUDGE
		j	lt,pf_det92
;get into low power mode......................

		@CLB	(RTC_ON)			;clear RTC display mode  for reduce backup current
		@CLB	(RTC_SET)			;clear RTC set mode
		call	init_io
;V2.00		clr	(TC1CR1).5			;00: stop and counter flag clear and overflow flag clear
;V2.00		clr	(TC1CR1).6			;
		clr	(EIRL).EF8			;TC1(Printer error check) interrupt disable(EF8)

		clr	(TC4CR).3			;TC4S=0(count stop)
		clr	(EIRH).EF11			;TC4(key scan) interrupt disable
		call	vft_disable		;V2.05
		@SEB	(F_DOFF)		;V2.09
		@BBS	(NO_CLK,pf_det00)		;V1.30
		clr	(TC3CR).4			;TC3S=0(count stop)
		clr	(EIRH).EF14			;TC3(interval TM & PF detection) interrupt disable
		ld	(SYSCR2),0y11100000		;V2.05;SYSCK=1(slow clock)	enter SLOW2 mode
		ld	(SYSCR2),0y01100000		;V2.05;XEN=0(stop main clock) enter SLOW1 mode
		ei					;V2.05
		ld	(SYSCR2),0y01100100		;V2.05;TGHALT=1(HALT TG) enter SLEEP0 mode
		jp	pf_det02			;V2.05;V1.30

pf_det00:
;	-----	wait until TBT interrupt occur -----
		@BBS	(NO_CLK,pf_det01)	;V2.05
		ei				;V2.05
		ld	(SYSCR2),0y01100100	;V2.05	;TGHALT=1(HALT TG) enter SLEEP0 mode
;				   |||| |______TGHAL=1: TG control is TG stops source clock to peripherals except TBT
;				   ||||________IDLE=1: CPU and watchdog timer are stopped (start SLEEP1/2 and IDLE1/2 mode)
;				   ||__________SYSCK=1: low-frequency clock
;				   |___________XEN=0: Turn off main oscillation
		jp	pf_det02		;V2.05
pf_det01:
;IDEL mode will be released by timer3 interrupt
		@BBS	(F_WAITP,pf_det02)	;V1.30
		@SEB	(F_WAITP)		;V1.30
		ei				;V1.30
		ld	(SYSCR1),0y01010100	;return to normal12 mode
;				   ||||||||____
;				   |||||______WUT=00: Warming-up time at release STOP mode 3X2^16/fc
;				   |||________OUTEN=0: Port output during STOP mode is high Impedance
;				   ||_________RELM=1: Rlease method for STOP mode is level-sensitive release
;				   |__________STOP=0: STOP mode not start, CPU core and pherals remain active
;
		ld	(SYSCR2),0y10010100	;V1.30	;TGHALT=1(HALT TG) enter IDLE1 mode
;				   |||| |______TGHAL=1: TG control is TG stops source clock to peripherals except TBT
;				   ||||________IDLE=1: CPU and watchdog timer are stopped (start SLEEP1/2 and IDLE1/2 mode)
;				   ||__________SYSCK=0: High-frequency clock
;				   |___________XEN=1: Turn on main oscillation

;resume from power failure mode................
pf_det02:	
		@BBS	(IO_PF,pf_det00)	;V1.30	;power failure?  yes->

		@BBS	(NO_CLK,pf_det_03)	;V1.30
		ld	(SYSCR2),0y11100000		;SYSCK=1(slow clock)	enter SLOW2 mode
		call	wait_wkup			;wait until main clock oscilated(approx.4ms)
		ld	(SYSCR2),0y11000000		;SYSCK=0(main clock)	enter NORMAL2 mode
		jp	pf_det_04	;V1.43
pf_det_03:
		call	wait_wkup		;V1.30	;wait until main clock oscilated(approx.4ms)
		ld	(SYSCR2),0y10000000	;V1.30	;SYSCK=0(main clock)	enter NORMAL1 mode
pf_det_04:
		call	init_io			;V1.43
		ld	sp,RAM_BOT		;V1.30	;stack pointer initial
		j	resume			;V1.30

pf_det90:
		ld	(PF_CNT),0
		@CLB	(F_WAITP)	;V1.30
pf_det92:
		@POP_REG
		reti

wait_40c:
wait_wkup:
		cmp	wa,(pc+a)	;\		;7 machine cycle(854us under 32.768KHz clock)
		cmp	wa,(pc+a)	;|
		cmp	wa,(pc+a)	;|no other mean, only delay 7 machine cycle every instruction
		cmp	wa,(pc+a)	;|
		cmp	wa,(pc+a)	;/
		ret

	end