ppc_cpu.h

SkyEye是一个可以运行嵌入式操作系统的硬件仿真工具

/*
 *	PearPC
 *	ppc_cpu.h
 *
 *	Copyright (C) 2003, 2004 Sebastian Biallas ([e-mail])
 *
 *	This program is free software; you can redistribute it and/or modify
 *	it under the terms of the GNU General Public License version 2 as
 *	published by the Free Software Foundation.
 *
 *	This program is distributed in the hope that it will be useful,
 *	but WITHOUT ANY WARRANTY; without even the implied warranty of
 *	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *	GNU General Public License for more details.
 *
 *	You should have received a copy of the GNU General Public License
 *	along with this program; if not, write to the Free Software
 *	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#ifndef __PPC_CPU_H__
#define __PPC_CPU_H__

#include <stddef.h>
#include <stdio.h>
#include "types.h"

#define PPC_MHz(v) ((v)*1000*1000)

#define TB_TO_PTB_FACTOR	10

#define PPC_MODEL "ppc_model"
#define PPC_CPU_MODEL "ppc_cpu"
#define PPC_CLOCK_FREQUENCY PPC_MHz(10)
#define PPC_BUS_FREQUENCY PPC_MHz(10)
#define PPC_TIMEBASE_FREQUENCY (PPC_CLOCK_FREQUENCY / TB_TO_PTB_FACTOR)

typedef union Vector_t {
	uint64 d[2];
	sint64 sd[2];
	float f[4];
	uint32 w[4];
	sint32 sw[4];
	uint16 h[8];
	sint16 sh[8];
	uint8 b[16];
	sint8 sb[16];
} Vector_t;

typedef struct ccsr_reg_s{
	uint32_t ccsr; /* Configuration,control and status registers base address register */
	uint32_t altcbar; /* allternate configuration base address register */
	uint32_t altcar; /* alternate configuration attribute register */
	uint32_t bptr; /* Boot page translation register */
}ccsr_reg_t;

/* Local bus controll register */
typedef struct lb_ctrl_s{
	uint32 br[8];
	//uint32 or[8];
	uint32 lcrr; /* Clock ratio register */
	//uint32 lbcr; /* Configuration register */
}lb_ctrl_t;

typedef struct law_reg_s{
	uint32_t lawbar[8];
	uint32_t lawar[8];
}law_reg_t;

typedef struct por_conf_s{
	uint32_t porpllsr;
	uint32_t porbmsr;
	uint32_t porimpscr;
	uint32_t pordevsr;
	uint32_t pordbgmsr;
	uint32_t gpporcr;
}por_conf_t;

/* 0x91a00-0x91a9f: SCC1-SCC4 */
typedef struct cpm_scc_s {
        uint32    gsmrl;
        uint32    gsmrh;
        uint16  psmr;
        char    res1[2];
        uint16  todr;
        uint16  dsr;
        uint16  scce;
        char    res2[2];
        uint16  sccm;
        char    res3;
        uint8  sccs;
        char    res4[8];
} cpm_scc_t;

typedef struct cpm_mux_s{
	uint32_t cmxfcr;
	uint32_t cmxscr;
} cpm_mux_t;
typedef struct cpm_ioport_s{
	uint32_t pdira;
	uint32_t ppara;
	uint32_t psora;
	uint32_t podra;
	uint32_t pdata;
	uint32_t pdirb;
        uint32_t pparb;
        uint32_t psorb;
        uint32_t podrb;
	uint32_t pdatb;
	uint32_t pdirc;
        uint32_t pparc;
        uint32_t psorc;
        uint32_t podrc;
	uint32_t pdatc;
	uint32_t pdird;
	uint32_t ppard;
	uint32_t psord;
	uint32_t podrd;
	uint32_t pdatd;
} cpm_ioport_t;

typedef struct cpm_reg_s{
	uint32_t cpcr;
	uint32_t rccr;
	uint32_t rter;
	uint32_t rtmr;
	uint32_t rtscr;
	uint32_t rtsr;
	
	byte *dpram;
	byte *iram; /* instruction RAM */
	cpm_scc_t scc[4];
	cpm_mux_t mux;
	uint32_t brgc[4];
	cpm_ioport_t ioport;
} cpm_reg_t;

typedef struct i2c_reg_s{
	uint32 i2cadr;
	uint32 i2ccr;
	uint32 i2csr;
	uint32 i2cdr;
	uint32 i2cfdr;
	uint32 i2cdfsrr;
}i2c_reg_t;

typedef struct debug_ctrl_s{
	uint32 clkocr;
	uint32 ddrdllcr;
	uint32 lbdrrcr;
}debug_ctrl_t;

typedef struct ppc_dma_s{
	uint32 satr0;
	uint32 datr0;
}mpc_dma_t;

typedef struct int_ctrl_s{
	uint32 sicr;
	uint32 sipnr_h;
	uint32 sipnr_l;
	uint32 scprr_h;
	uint32 scprr_l;
	uint32 simr_h;
	uint32 simr_l;
}int_ctrl_t;

typedef struct ddr_ctrl_s{
	uint32 err_disable;
}ddr_ctrl_t;

typedef struct l2_reg_s{
	uint32 l2ctl;
}l2_reg_t;

typedef struct pci_cfg_s{
	uint32 cfg_addr;
	uint32 cfg_data;
	uint32 int_ack;
}pci_cfg_t;

typedef struct pci_atmu_s{
	uint32 potar1;
	uint32 potear1;
	uint32 powbar1;
	uint32 reserv1;
	uint32 powar1;
}pci_atmu_t;

typedef struct pic_global_s{
	uint32 gcr;
	uint32 frr;
	uint32 tfrr;
	uint32 gtdr0;
	uint32 gtdr1;
	uint32 gtdr2;
	uint32 gtdr3;
	uint32 gtvpr0;
	uint32 gtvpr1;
	uint32 gtvpr2;
	uint32 gtvpr3;
	uint32 svr;
	uint32 iack;
}pic_global_t;

typedef struct pic_ram_s{
	uint32 eivpr[11];
	uint32 eidr[11];
	uint32 ctpr0;
	uint32 iivpr[32];
	uint32 iidr[32];
}pic_ram_t;

typedef struct pic_percpu_s{
	uint32 iack0;
}pic_percpu_t;

typedef struct PPC_CPU_State_s {	
	// * uisa
	uint32 gpr[32];
	uint64 fpr[32];
	uint32 cr;
	uint32 fpscr;
	uint32 xer;	// spr 1
	uint32 xer_ca;  // carry from xer
	uint32 lr;	// spr 8
	uint32 ctr;	// spr 9
	// * oea
	uint32 msr;
	uint32 pvr;	// spr 287

	//    * memory managment
	uint32 ibatu[4];	// spr 528, 530, 532, 534
	uint32 ibatl[4];	// spr 529, 531, 533, 535
	uint32 ibat_bl17[4];	// for internal use

	uint32 dbatu[4];	// spr 536, 538, 540, 542
	uint32 dbatl[4];	// spr 537, 539, 541, 543
	uint32 dbat_bl17[4];	// for internal use

	uint32 sdr1;	// spr 25       (page table base address)

	uint32 sr[16];
	
	//    * exception handling
	uint32 dar;	// spr 19
	uint32 dsisr;	// spr 18
	uint32 sprg[8]; // spr 272-275
	//uint32 sprg[4];
	uint32 srr[2];	// spr 26-27
	
	//    * misc
	uint32 dec;	// spr 22
	uint32 ear;	// spr 282 .101
	uint32 pir;	// spr 1032
	uint64 tb;	// .75 spr 284(l)/285(u)
	
	uint32 hid[16];
	// * internal
	
	uint32 pc;
	uint32 npc;
	uint32 current_opc;
	bool   exception_pending;
	bool   dec_exception;
	bool   ext_exception;
	bool   stop_exception;
	bool   singlestep_ignore;

	uint32 pagetable_base;
	int    pagetable_hashmask;
	uint32 reserve;
	bool   have_reservation;
	
	// for generic cpu core
	uint32 effective_code_page;
	byte  *physical_code_page;
	uint64 pdec;	// more precise version of dec
	uint64 ptb;	// more precise version of tb

	// for altivec
	uint32 vscr;
	uint32 vrsave;	// spr 256
	Vector_t vr[36];		// <--- this MUST be 16-byte alligned
	uint32 vtemp;
	/* e500 specific register */
	uint32 l1csr[2]; /* L1 cache constrol and status */
	uint32 csrr[2]; /* Critical save/restore register */
	uint32 mcsrr[2]; /* Machine check save/restore register */
	uint32 esr; /* Exception syndrome register */
	uint32 mcsr; /* Machine check syndrome register */
	uint32 dear; /* Data exception address register */
	uint32 dbcr[3]; /* Debug control register */
	uint32 dbsr; /* Debug status register */ 
	uint32 pid[3]; /* Process ID */
	uint32 tcr; /* Timer control register */
	uint32 tsr; /* Timer status register */
	uint32 dac[2]; /* Data address compare */
	uint32 ivpr; /* Interrupt vector */
	uint32 ivor[16]; /* 0 = Critical input */
	uint32 iac[2]; /* Instruction address compare */

	uint32 tbl;
	uint32 tbu;

	uint32 spefscr;

	ccsr_reg_t ccsr;
	law_reg_t law; /* Local access window */
	lb_ctrl_t lb_ctrl; /* Local bus controll register */
	cpm_reg_t cpm_reg; /* Communication processor */
	uint32 sccr; /* System clock control register */
	por_conf_t por_conf;
	i2c_reg_t i2c_reg;
	debug_ctrl_t debug_ctrl;
	ddr_ctrl_t ddr_ctrl;
	mpc_dma_t dma;
	l2_reg_t l2_reg;
	pci_cfg_t pci_cfg;
	pci_atmu_t pci_atmu;
	pic_global_t pic_global;
	int_ctrl_t int_ctrl;
	pic_ram_t pic_ram;
	pic_percpu_t pic_percpu;
}PPC_CPU_State;
extern PPC_CPU_State gCPU;

#define E500

/*
cr: .67
 0- 3 cr0
 4- 7 cr1
 8-11 cr2
12-15 cr3
16-19 cr4
20-23 cr5
24-27 cr6
28-31 cr7
*/

#define CR_CR0(v) ((v)>>28)
#define CR_CR1(v) (((v)>>24)&0xf)
#define CR_CRx(v, x) (((v)>>(4*(7-(x))))&0xf)

/*
cr0 bits: .68