ppc_mmu.c

SkyEye是一个可以运行嵌入式操作系统的硬件仿真工具

						return r;
					case 0x90C14:
						gCPU.int_ctrl.scprr_h = data;
						return r;
					case 0x90C18:
						gCPU.int_ctrl.scprr_l = data;
						return r;
					case 0x90C1C:
						gCPU.int_ctrl.simr_h = data;
						return r;
					case 0x90C20:
						gCPU.int_ctrl.simr_l = data;
						return r;
                                        default:
                                                fprintf(stderr,"in %s, error when write interrupt controller,offset=0x%x,pc=0x%x\n",__FUNCTION__, offset, gCPU.pc);
                         	                return r;
				}
			}

			if(offset >= 0x919C0 && offset <= 0x919E0){
				switch(offset){
					case 0x919C0:
						gCPU.cpm_reg.cpcr = data;
						/* set FLG bit to zero, that means we are ready for new command*/
						/* get sub block code */
						if((0x1f & (gCPU.cpm_reg.cpcr >> 21)) == 0x4){
							;/* we */	
							if((0xf & gCPU.cpm_reg.cpcr) == 0x0){
							/* INIT Rx and Tx Param in SCC1 */
							}
						}
						gCPU.cpm_reg.cpcr &= ~(1 << 16);
						return r;
					default:
						fprintf(stderr,"in %s, error when write cpm,offset=0x%x,pc=0x%x\n",__FUNCTION__, offset, gCPU.pc);
						return r;
				}
			}
			if(offset >= 0x91A00 && offset <= 0x91A3F){
                                int i = (0x20 & offset) >> 5;
                                offset = 0x1f & offset;
                                switch(offset){
                                        case 0x0:
                                                gCPU.cpm_reg.scc[i].gsmrl = data;
						if(gCPU.cpm_reg.scc[i].gsmrl & 0x00000020)
                                                        ; /* Enable Receive */
                                                if(gCPU.cpm_reg.scc[i].gsmrl & 0x00000010)
                                                        ; /* Enable Transmit */

                                                return r;
                                        case 0x4:
                                                gCPU.cpm_reg.scc[i].gsmrh = data;
                                                return r;
                                        case 0x8:
                                                gCPU.cpm_reg.scc[i].psmr = data;
                                                return r;
                                        case 0xE:
                                                gCPU.cpm_reg.scc[i].dsr = data;
                                                return r;
                                        case 0x14:
                                                gCPU.cpm_reg.scc[i].sccm = data;
                                                return r;

                                        case 0x10: /* W1C */
                                                gCPU.cpm_reg.scc[i].scce &= ~data;
                                                return r;
                                        default:
                                                fprintf(stderr,"in %s, error when read CCSR.offset=0x%x, \
                                pc=0x%x\n",__FUNCTION__, offset, gCPU.pc);

                                                skyeye_exit(-1);

                                }
                        }

			/* CPM MUX I/O */
			if(offset >= 0x91B00 && offset <= 0x91B1F){
				switch(offset){
					case 0x91B04:
                                                gCPU.cpm_reg.mux.cmxfcr = data;
                                                return r;
                                        case 0x91B08:
                                                gCPU.cpm_reg.mux.cmxscr = data;
                                                return r;
                                        default:
                                                fprintf(stderr,"in %s, error when read CCSR.offset=0x%x, \
                                pc=0x%x\n",__FUNCTION__, offset, gCPU.pc);

                                                skyeye_exit(-1);

                                }

			}
			/* Input/Output port */
                        if(offset >= 0x90D00 && offset <= 0x90D70){
                                switch(offset){
					case 0x90D00:
                                                gCPU.cpm_reg.ioport.pdira = data;
                                                return r;

                                        case 0x90D04:
                                                gCPU.cpm_reg.ioport.ppara = data;
                                                return r;
					case 0x90D08:
                                                gCPU.cpm_reg.ioport.psora = data;
                                                return r;
					case 0x90D0C:
						gCPU.cpm_reg.ioport.podra = data;
						return r;
					case 0x90D10:
                                                gCPU.cpm_reg.ioport.pdata = data;
                                                return r;
					case 0x90D20:
						gCPU.cpm_reg.ioport.pdirb = data;
						return r;
					case 0x90D24:
						gCPU.cpm_reg.ioport.pparb = data;
						return r;
					case 0x90D28:
						gCPU.cpm_reg.ioport.psorb = data;
						return r;
					case 0x90D40:
						gCPU.cpm_reg.ioport.pdirc = data;
						return r;
					case 0x90D44:
						gCPU.cpm_reg.ioport.pparc = data;
						return r;
					case 0x90D48:
						gCPU.cpm_reg.ioport.psorc = data;
						return r;
					case 0x90D60:
                                                gCPU.cpm_reg.ioport.pdird = data;
                                                return r;
                                        case 0x90D64:
                                                gCPU.cpm_reg.ioport.ppard = data;
                                                return r;
                                        case 0x90D68:
                                                gCPU.cpm_reg.ioport.psord = data;
                                                return r;

                                        default:
                                                fprintf(stderr,"in %s, error when write io port.offset=0x%x, \
                                pc=0x%x\n",__FUNCTION__, offset, gCPU.pc);
						return r;
                                                //skyeye_exit(-1);

                                }

                        }
						/* BRG */
			if(offset >= 0x919F0 && offset <= 0x919FC){
				gCPU.cpm_reg.brgc[(offset - 0x919F0)/4] = data;
                                return r;

			}
			if(offset >= 0x80000 && offset < 0x8C000){
				 //fprintf(prof_file,"DBG_CPM:in %s,offset=0x%x,data=0x%x,pc=0x%x\n",__FUNCTION__, offset, data, gCPU.pc);

                                *((sint32 *)&gCPU.cpm_reg.dpram[offset - 0x80000]) = ppc_word_to_BE(data);
                                return r;
                        }
			if(offset >= 0x8C00 && offset <= 0x8DFC)
			{
				switch(offset){
				case 0x8C20:
					gCPU.pci_atmu.potar1 = data;
					return r;
				case 0x8C24:
					gCPU.pci_atmu.potear1 = data;
					return r;
				case 0x8C28:
					gCPU.pci_atmu.powbar1 = data;
					return r;
				case 0x8C2C:
					gCPU.pci_atmu.reserv1 = data;
					return r;
				case 0x8C30:
					gCPU.pci_atmu.powar1 = data;
					return r;
				default:
					fprintf(stderr,"in %s, error when write to PCI_ATMU.offset=0x%x,pc=0x%x\n",__FUNCTION__,offset,gCPU.pc);
					//skyeye_exit(-1);
					return r;
				}
			}
			if(offset >= 0x40000 && offset <= 0x4FFF0){
				switch(offset){
                                        case 0x41020:
                                                /* source a
ttribute register for DMA0 */
                                                gCPU.pic_global.gcr = data;
                                                return r;
					case 0x410e0:
						gCPU.pic_global.svr = data;
						return r;
					case 0x41120:
                                                gCPU.pic_global.gtvpr0 = data;
                                                return r;
					case 0x41130:
						gCPU.pic_global.gtdr0 = data;
						return r;
					case 0x41160:
						gCPU.pic_global.gtvpr1 = data;
						return r;
					case 0x41170:
						gCPU.pic_global.gtdr1 = data;		
						return r;
					case 0x411a0:
						gCPU.pic_global.gtvpr2 = data;
						return r;
					case 0x411B0:
						gCPU.pic_global.gtdr2 = data;
						return r;
					case 0x411E0:
						gCPU.pic_global.gtvpr3 = data;
						return r;
					case 0x411F0:
						gCPU.pic_global.gtdr3 = data;
						return r;
                                        default:
                                                fprintf(stderr,"in %s, error when write global.offset=0x%x,pc=0x%x\n",__FUNCTION__, offset, gCPU.pc);
                                                return r;
                                                //skyeye_ex
it(-1);

                                }

			}

			switch(offset){
				case 0x0:
					gCPU.ccsr.ccsr = data;
					break;
				 case 0x90C80:
                                        gCPU.sccr = data;
                                        break;
				case 0x50D4:
                                        gCPU.lb_ctrl.lcrr = data;
                                        return r;
				case 0x3008:
					gCPU.i2c_reg.i2ccr = data;
					return r;
				case 0xe0e10:
                                        gCPU.debug_ctrl.ddrdllcr = data;
                                        return r;
				case 0x8000:
					gCPU.pci_cfg.cfg_addr = data;
					return r;
				case 0x8004:
                                        gCPU.pci_cfg.cfg_data = data;
                                        return r;

				default:
					fprintf(stderr,"in %s, error when write to CCSR.offset=0x%x,pc=0x%x\n",__FUNCTION__, offset, gCPU.pc);
					//skyeye_exit(-1);
			}
		}
		else if((p >= boot_rom_start_addr) && (p < (boot_rom_start_addr + boot_romSize )))

                        *((int *)&boot_rom[p - boot_rom_start_addr]) = ppc_word_to_BE(data);
		else if((p >= init_ram_start_addr) && (p < (init_ram_start_addr + init_ram_size)))
			*((int *)&init_ram[p - init_ram_start_addr]) = ppc_word_to_BE(data);
		else if((p >= 0x0) && (p < (0x0 + DDR_RAM_SIZE))){
			*((int *)&ddr_ram[p]) = ppc_word_to_BE(data);
			}
                else{
                        fprintf(stderr,"in %s, can not find address 0x%x,pc=0x%x\n", __FUNCTION__, p, gCPU.pc);
                        //skyeye_exit(-1);
                }
	}
	return r;
}

int FASTCALL ppc_write_effective_half(uint32 addr, uint16 data)
{	
	uint32 p;
	int r;
	if (!((r=ppc_effective_to_physical(addr, PPC_MMU_WRITE, &p)))) {
		//printf("DBG:in %s,addr=0x%x,p=0x%x, data=0x%x\n", __FUNCTION__, addr,p, data);
		//printf("DBG:ccsr=0x%x,CCSR_BASE=0x%x",gCPU.ccsr.ccsr,GET_CCSR_BASE(gCPU.ccsr.ccsr));
		if(p >= GET_CCSR_BASE(gCPU.ccsr.ccsr) && p <(GET_CCSR_BASE(gCPU.ccsr.ccsr) + CCSR_MEM_SIZE)){
			int offset = p - GET_CCSR_BASE(gCPU.ccsr.ccsr);
			//printf("DBG:write to CCSR,value=0x%x,offset=0x%x,pc=0x%x\n", data, offset,gCPU.pc);
			if(offset >= 0xC08 && offset <= 0xCF0){
				if(offset & 0x8){
					gCPU.law.lawbar[(offset - 0xC08)/0x20] = data;
				}else{
					gCPU.law.lawar[(offset - 0xC10)/0x20] = data;
				}
				return r;
			}
			if(offset >= 0x5000 && offset <= 0x5038){
				gCPU.lb_ctrl.br[(offset - 0x5000)/0x8] = data;
				return r;
			}
			if(offset >= 0x91A00 && offset <= 0x91A3F){
				int i = (0x20 & offset) >> 5;
				offset = 0x1f & offset;
                                switch(offset){
                                        case 0x0:
                                                gCPU.cpm_reg.scc[i].gsmrl = data;
                                                return r;
					case 0x4:
						gCPU.cpm_reg.scc[i].gsmrh = data;
						return r;
					case 0x8:
						gCPU.cpm_reg.scc[i].psmr = data;
                                                return r;
					case 0xE:
						gCPU.cpm_reg.scc[i].dsr = data;
						return r;
					case 0x14:
						gCPU.cpm_reg.scc[i].sccm = data;
						return r;
						
					case 0x10: /* W1C */
						gCPU.cpm_reg.scc[i].scce &= ~data;
						return r;
                                        default:
                                                fprintf(stderr,"in %s, error when read CCSR.offset=0x%x, \
                                pc=0x%x\n",__FUNCTION__, offset, gCPU.pc);

                                                skyeye_exit(-1);

                                }
                        }
			if(offset >= 0x919C0 && offset <= 0x919E0){
				switch(offset){
					case 0x919C0:
						gCPU.cpm_reg.cpcr = data;
						return r;
					default:
                                        	fprintf(stderr,"in %s, error when write to CCSR.offset=0x%x,pc=0x%x\n",__FUNCTION__,offset,gCPU.pc);
                                        	//skyeye_exit(-1);

				}
			}
			if(offset >= 0x80000 && offset < 0x8C000){
				//fprintf(prof_file,"DBG_CPM:in %s,offset=0x%x,data=0x%x,pc=0x%x\n",__FUNCTION__, offset, data, gCPU.pc);
                                *((sint16 *)&gCPU.cpm_reg.dpram[offset - 0x80000]) = ppc_half_to_BE(data);
                                return r;
                        }

			switch(offset){
				case 0x0:
					gCPU.ccsr.ccsr = data;
					break;
				case 0x90C00:
					gCPU.int_ctrl.sicr = data;
					break;
				case 0x90C80:
                                        gCPU.sccr = data;
                                        break;
				case 0x8004:
					gCPU.pci_cfg.cfg_data = data;
					break;
				case 0x8006:
					gCPU.pci_cfg.cfg_data = data;
					break;
				default:
					fprintf(stderr,"in %s, error when write to CCSR.offset=0x%x,pc=0x%x\n",__FUNCTION__,offset,gCPU.pc);
					//skyeye_exit(-1);
			}
		}
		else if((p >= boot_rom_start_addr) && (p < (boot_rom_start_addr + boot_romSize )))

                        *((sint16 *)&boot_rom[p - boot_rom_start_addr]) = ppc_half_to_BE(data);
		else if((p >= init_ram_start_addr) && (p < (init_ram_start_addr + init_ram_size)))
			*((sint16 *)&init_ram[p - init_ram_start_addr]) = ppc_half_to_BE(data);
		else if((p >= 0x0) && (p < (0x0 + DDR_RAM_SIZE))){
                        *((sint16 *)&ddr_ram[p]) = ppc_half_to_BE(data);
		}
                else{
                        fprintf(stderr,"in %s, can not find address 0x%x,pc=0x%x\n", __FUNCTION__, p, gCPU.pc);
                        //skyeye_exit(-1);
                }
	}
	return r;
}

int FASTCALL ppc_write_effective_byte(uint32 addr, uint8 data)
{
	uint32 p;
        int r;
        if (!((r=ppc_effective_to_physical(addr, PPC_MMU_WRITE, &p)))) {