ppc_mmu.c

SkyEye是一个可以运行嵌入式操作系统的硬件仿真工具

                                                *result = gCPU.cpm_reg.ioport.pparb;
                                                return r;
                                        case 0x90D28:
                                                *result = gCPU.cpm_reg.ioport.psorb;
                                                return r;
                                        case 0x90D40:
                                                *result = gCPU.cpm_reg.ioport.pdirc;
                                                return r;
                                        case 0x90D44:
                                                *result = gCPU.cpm_reg.ioport.pparc;
                                                return r;
                                        case 0x90D48:
                                                *result = gCPU.cpm_reg.ioport.psorc;
                                                return r;
					case 0x90D60:
                                                *result = gCPU.cpm_reg.ioport.pdird;
                                                return r;
                                        case 0x90D64:
                                                *result = gCPU.cpm_reg.ioport.ppard;
                                                return r;
                                        case 0x90D68:
                                                *result = gCPU.cpm_reg.ioport.psord;
                                                return r;


                                        default:
                                                fprintf(stderr,"in %s, error when read IO port.offset=0x%x, \
                                pc=0x%x\n",__FUNCTION__, offset, gCPU.pc);
						return r;
                                                //skyeye_exit(-1);

                                }

                        }

			if(offset >= 0x80000 && offset < 0x8C000){
                                *result = ppc_word_from_BE(*((sint32 *)&gCPU.cpm_reg.dpram[offset - 0x80000]));
				//printf("DBG_CPM:in %s,offset=0x%x,data=0x%x,pc=0x%x\n",__FUNCTION__, offset, *result,gCPU.pc);
                                return r;
                        }

			if(offset >= 0xE0000 && offset <= 0xE0020){
				switch(offset){
                                	case 0xE0000:
                                                *result = gCPU.por_conf.porpllsr;
                                                return r;
					case 0xE000C:
						*result = gCPU.por_conf.pordevsr;
						return r;

                                        default:
                                                fprintf(stderr,"in %s, error when read CCSR.addr=0x%x,pc=0x%x\n",__FUNCTION__, addr, gCPU.pc);
                                                skyeye_exit(-1);
                                }

			}
                        switch(offset){
                                case 0x0:
                                        *result = gCPU.ccsr.ccsr;
                                        break;
				case 0xC28:
					*result = gCPU.law.lawbar[1];
					break;
				case 0xC30:
					*result = gCPU.law.lawar[1];
				case 0x90C80:
					*result = gCPU.sccr;
					break;
				case 0xe0e10:
					*result = gCPU.debug_ctrl.ddrdllcr;
					return r;	
				case 0x50D4:
					*result = gCPU.lb_ctrl.lcrr;
					return r;
				case 0x20000:
					*result = gCPU.l2_reg.l2ctl;
					return r;
				case 0x8004:
                                        *result = gCPU.pci_cfg.cfg_data;
                                        return r;
				default:
                                        fprintf(stderr,"in %s, error when read CCSR.offset=0x%x,pc=0x%x\n", __FUNCTION__, offset, gCPU.pc);
                                        //skyeye_exit(-1);
                        }
		}
		else if((p >= boot_rom_start_addr) && (p < (boot_rom_start_addr - 1 + boot_romSize )))
			*result = ppc_word_from_BE(*((int *)&boot_rom[p - boot_rom_start_addr]));
		else if((p >= init_ram_start_addr) && (p < (init_ram_start_addr + init_ram_size)))
                        *result = ppc_word_from_BE(*((int *)&init_ram[p - init_ram_start_addr]));
		else if((p >= 0x0) && (p < (0x0 + DDR_RAM_SIZE))){
			                        *result = ppc_word_from_BE(*((int *)&ddr_ram[p]));
		}
		else{
			fprintf(stderr,"in %s, can not find address 0x%x,pc=0x%x\n", __FUNCTION__, p, gCPU.pc);
			//skyeye_exit(-1);
		}	
	}
	return r;
}

int FASTCALL ppc_read_effective_half(uint32 addr, uint16 *result)
{
	uint32 p;
	int r;
	if (!(r = ppc_effective_to_physical(addr, PPC_MMU_READ, &p))) {
		//printf("DBG:ccsr=0x%x,CCSR_BASE=0x%x\n",gCPU.ccsr.ccsr,GET_CCSR_BASE(gCPU.ccsr.ccsr));
		if((p >= GET_CCSR_BASE(gCPU.ccsr.ccsr)) && (p < (GET_CCSR_BASE(gCPU.ccsr.ccsr) + CCSR_MEM_SIZE))){
			int offset = p - GET_CCSR_BASE(gCPU.ccsr.ccsr);
			//printf("DBG:read CCSR,offset=0x%x,pc=0x%x\n", offset, gCPU.pc);
			if(offset >= 0x919C0 && offset <= 0x919E0){
                                switch(offset){
                                        case 0x919C0:
                                                *result = gCPU.cpm_reg.cpcr;
                                                return r;
                                        default:
	                                        fprintf(stderr,"in %s, error when read CCSR.offset=0x%x,pc=0x%x\n",__FUNCTION__, offset, gCPU.pc);
                                        	skyeye_exit(-1);
                                }
                        }
			if((offset >= 0x80000) && (offset < 0x8C000)){
				*result = ppc_half_from_BE(*((sint16 *)&gCPU.cpm_reg.dpram[offset - 0x80000]));
				return r;
			}
			if(offset >= 0x91A00 && offset <= 0x91A3F){
                                int i = (0x20 & offset) >> 5;
                                offset = 0x1f & offset;
                                switch(offset){
                                        case 0x0:
                                                *result = gCPU.cpm_reg.scc[i].gsmrl;
                                                return r;
                                        case 0x4:
                                                *result = gCPU.cpm_reg.scc[i].gsmrh;
                                                return r;
                                        case 0x8:
                                                *result = gCPU.cpm_reg.scc[i].psmr;
                                                return r;
                                        case 0xE:
                                                *result = gCPU.cpm_reg.scc[i].dsr;
                                                return r;
                                        case 0x14:
                                                *result = gCPU.cpm_reg.scc[i].sccm;
                                                return r;

                                        case 0x10: /* W1C */
                                                *result = gCPU.cpm_reg.scc[i].scce;
                                                return r;
                                        default:
                                                fprintf(stderr,"in %s, error when read CCSR.offset=0x%x, \
                                pc=0x%x\n",__FUNCTION__, offset, gCPU.pc);

                                                skyeye_exit(-1);

                                }
                        }
	
			if(offset >= 0xE0000 && offset <= 0xE0020){
				switch(offset){
                                	case 0xE0000:
                                                *result = gCPU.por_conf.porpllsr;
                                                return r;
                                        default:
                                                fprintf(stderr,"in %s, error when read CCSR.offset=0x%x,pc=0x%x\n",__FUNCTION__, offset, gCPU.pc);
                                                skyeye_exit(-1);
                                }

			}
                        switch(offset){
                                case 0x0:
                                        *result = gCPU.ccsr.ccsr;
                                        break;
				case 0x90C80:
					*result = gCPU.sccr;
					break;
				case 0x8004:
					*result = gCPU.pci_cfg.cfg_data;
					break;	
				case 0x8006:
                                        *result = gCPU.pci_cfg.cfg_data;
                                        break;
                                default:
                                        fprintf(stderr,"in %s, error when read CCSR.offset=0x%x,pc=0x%x\n",__FUNCTION__,offset,gCPU.pc);
                                        //skyeye_exit(-1);
                        }
		}
		else if((p >= boot_rom_start_addr) && (p < (boot_rom_start_addr - 1 + boot_romSize )))
			*result = ppc_half_from_BE(*((sint16 *)&boot_rom[p - boot_rom_start_addr]));
			
		else if((p >= init_ram_start_addr) && (p < (init_ram_start_addr + init_ram_size)))
                        *result = ppc_half_from_BE(*((sint16 *)&init_ram[p - init_ram_start_addr]));
		else if((p >= 0x0) && (p < (0x0 + DDR_RAM_SIZE)))
{
                        *result = ppc_half_from_BE(*((sint16 *)&ddr_ram[p]));
                }
		else{
			fprintf(stderr,"in %s, can not find address 0x%x,pc=0x%x\n", __FUNCTION__, p, gCPU.pc);
			//skyeye_exit(-1);
		}	
	}
	return r;
}

int FASTCALL ppc_read_effective_byte(uint32 addr, uint8 *result)
{ 
	uint32 p;
	int r;
	if (!(r = ppc_effective_to_physical(addr, PPC_MMU_READ, &p))) {
		//printf("\nDBG:in %s,addr=0x%x,p=0x%x\n", __FUNCTION__, addr,p);
		//printf("DBG:ccsr=0x%x,CCSR_BASE=0x%x\n",gCPU.ccsr.ccsr,GET_CCSR_BASE(gCPU.ccsr.ccsr));
		if((p >= GET_CCSR_BASE(gCPU.ccsr.ccsr)) && (p < (GET_CCSR_BASE(gCPU.ccsr.ccsr) + CCSR_MEM_SIZE))){
			int offset = p - GET_CCSR_BASE(gCPU.ccsr.ccsr);
			//printf("DBG:read CCSR,offset=0x%x,pc=0x%x\n", offset, gCPU.pc);
			if(offset >= 0x919C0 && offset <= 0x919E0){
                                switch(offset){
                                        case 0x919C0:
                                                *result = gCPU.cpm_reg.cpcr;
                                                return r;
                                        default:
	                                        fprintf(stderr,"in %s, error when read CCSR.addr=0x%x,pc=0x%x\n",__FUNCTION__, addr, gCPU.pc);
                                        	skyeye_exit(-1);
                                }
                        }
			if(offset >= 0x80000 && offset < 0x8C000){
				*result = *((sint16 *)&gCPU.cpm_reg.dpram[offset - 0x80000]);
				//printf("DBG_CPM:in %s,offset=0x%x,data=0x%x,pc=0x%x\n",__FUNCTION__, offset, *result,gCPU.pc);
				return r;
			}
	
			if(offset >= 0xE0000 && offset <= 0xE0020){
				switch(offset){
                                	case 0xE0000:
                                                *result = gCPU.por_conf.porpllsr;
                                                return r;
                                        default:
                                                fprintf(stderr,"in %s, error when read CCSR.addr=0x%x,pc=0x%x\n",__FUNCTION__, addr, gCPU.pc);
                                                skyeye_exit(-1);
                                }

			}
                        switch(offset){
                                case 0x0:
                                        *result = gCPU.ccsr.ccsr;
                                        break;
				case 0x90C80:
					*result = gCPU.sccr;
					break;
				case 0x300C:
					*result = gCPU.i2c_reg.i2csr;
					fprintf(prof_file,"KSDBG:read i2csr result=0x%x\n", *result);
					return r;
				case 0x8006:
					*result = gCPU.pci_cfg.cfg_data;
					return r;
                                default:
					return r;
                                        //fprintf(stderr,"in %s, error when read CCSR.addr=0x%x,pc=0x%x\n",__FUNCTION__,addr,gCPU.pc);
                                        //skyeye_exit(-1);
                        }
		}
		else if((p >= boot_rom_start_addr) && (p < (boot_rom_start_addr - 1 + boot_romSize )))
			*result = *((byte *)&boot_rom[p - boot_rom_start_addr]);
		else if((p >= init_ram_start_addr) && (p < (init_ram_start_addr + init_ram_size)))
                        *result = *((byte *)&init_ram[p - init_ram_start_addr]);
		else if((p >= 0x0) && (p < (0x0 + DDR_RAM_SIZE))){
                        *result = *((byte *)&ddr_ram[p]);
                }
		else{
			fprintf(stderr,"in %s, can not find address 0x%x,pc=0x%x\n", __FUNCTION__, p, gCPU.pc);
			skyeye_exit(-1);
		}	
	}
	return r;
}


int FASTCALL ppc_write_effective_word(uint32 addr, uint32 data)
{
	uint32 p;
	int r;
	if (!((r=ppc_effective_to_physical(addr, PPC_MMU_WRITE, &p)))) {
		if(p >= GET_CCSR_BASE(gCPU.ccsr.ccsr) && p <(GET_CCSR_BASE(gCPU.ccsr.ccsr) + CCSR_MEM_SIZE)){
			int offset = p - GET_CCSR_BASE(gCPU.ccsr.ccsr);
			//printf("DBG:write to CCSR,value=0x%x,offset=0x%x,pc=0x%x\n", data, offset,gCPU.pc);
			if(offset >= 0xC08 && offset <= 0xCF0){
				if(offset & 0x8){
					gCPU.law.lawbar[(offset - 0xC08)/0x20] = data;
				}else{
					gCPU.law.lawar[(offset - 0xC10)/0x20] = data;
				}
				return r;
			}

			if(offset >= 0x2000 && offset <= 0x2E58){
                                switch(offset){
                                        case 0x2E44:
                                                gCPU.ddr_ctrl.err_disable = data;
                                                return r;
                                        default:
                                                fprintf(stderr,"in %s, error when write ddr_ctrl,offset=0x%x,pc=0x%x\n",__FUNCTION__, offset, gCPU.pc);
                                                skyeye_exit(-1);
                                }
                        }

			if(offset >= 0x5000 && offset <= 0x50D4){
				if(offset >= 0x5000 && offset <= 0x5038){
					gCPU.lb_ctrl.br[(offset - 0x5000)/0x8] = data;
					return r;
				}
#if 0
				switch(offset){
                                        case 0x50D0:
                                                gCPU.lb_ctrl.lbcr = data;
                                                return r;
                                        default:
                                                fprintf(stderr,"in %s, error when read CCSR.addr=0x%x, \
                                pc=0x%x\n",__FUNCTION__, addr, gCPU.pc);

                                                skyeye_exit(-1);

                                }
#endif
				
                               fprintf(stderr,"in %s, error when write lb_ctrl.addr=0x%x, \
                                pc=0x%x\n",__FUNCTION__, addr, gCPU.pc);

				return r;
			}
			
			/* DMA */
			if(offset >= 0x21100 && offset <= 0x21300){
				switch(offset){
					case 0x21110:
						/* source attribute register for DMA0 */
						gCPU.dma.satr0 = data;
						return r;
					case 0x21118:
						gCPU.dma.satr0 = data;
						return r;
					default:
                                                fprintf(stderr,"in %s, error when write dma.addr=0x%x, \
                                pc=0x%x\n",__FUNCTION__, addr, gCPU.pc);
						return r;
                                                //skyeye_exit(-1);

				}
			}

			/**
 			 *  PIC Register Address Map
			 */
			if(offset >= 0x50000 && offset <= 0x600B0){
				if(offset >= 0x50000 && offset <= 0x50170){
					int index = (offset - 0x50000) >> 4;
					if(index & 0x1)
						gCPU.pic_ram.eidr[index >> 1] = data;
					else
						gCPU.pic_ram.eivpr[index >> 1] = data;
					return r;
				}
				if(offset >= 0x50200 && offset <= 0x505F0){
                                        int index = (offset - 0x50200) >> 4;
					return r;
                                }

                                switch(offset){
					case 0x60080:
                                                gCPU.pic_ram.ctpr0 = data;
                                                return r;

                                        default:
                                                fprintf(stderr,"in %s, error when write pic ram,offset=0x%x,pc=0x%x\n",__FUNCTION__, offset, gCPU.pc);
						return r;
				}
                        }

			/**
			 * Interrupt Controller
			 */

			if(offset >= 0x90C00 && offset <= 0x90C7F){
                                switch(offset){
                                        case 0x90C08: /* W1C */
						gCPU.int_ctrl.sipnr_h &= ~data;
                                                return r;
					case 0x90C0C: /* W1C */
						gCPU.int_ctrl.sipnr_l &= ~data;