ppc_vec.c

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void ppc_opc_vaddubm()
{
	VECTOR_DEBUG;
	int vrD, vrA, vrB;
	uint8 res;
	PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB);
	int i;
	for (i=0; i<16; i++) {
		res = gCPU.vr[vrA].b[i] + gCPU.vr[vrB].b[i];
		gCPU.vr[vrD].b[i] = res;
	}
}

/*	vadduhm		Vector Add Unsigned Half Word Modulo
 *	v.143
 */
void ppc_opc_vadduhm()
{
	VECTOR_DEBUG;
	int vrD, vrA, vrB;
	uint16 res;
	PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB);
	int i;
	for (i=0; i<8; i++) {
		res = gCPU.vr[vrA].h[i] + gCPU.vr[vrB].h[i];
		gCPU.vr[vrD].h[i] = res;
	}
}

/*	vadduwm		Vector Add Unsigned Word Modulo
 *	v.145
 */
void ppc_opc_vadduwm()
{
	VECTOR_DEBUG;
	int vrD, vrA, vrB;
	uint32 res;
	PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB);
	int i;
	for (i=0; i<4; i++) {
		res = gCPU.vr[vrA].w[i] + gCPU.vr[vrB].w[i];
		gCPU.vr[vrD].w[i] = res;
	}
}

/*	vaddfp		Vector Add Float Point
 *	v.137
 */
void ppc_opc_vaddfp()
{
	VECTOR_DEBUG;
	int vrD, vrA, vrB;
	float res;
	PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB);
	int i;
	for (i=0; i<4; i++) { //FIXME: This might not comply with Java FP
		res = gCPU.vr[vrA].f[i] + gCPU.vr[vrB].f[i];
		gCPU.vr[vrD].f[i] = res;
	}
}

/*	vaddcuw		Vector Add Carryout Unsigned Word
 *	v.136
 */
void ppc_opc_vaddcuw()
{
	VECTOR_DEBUG;
	int vrD, vrA, vrB;
	uint32 res;
	PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB);
	int i;
	for (i=0; i<4; i++) {
		res = gCPU.vr[vrA].w[i] + gCPU.vr[vrB].w[i];
		gCPU.vr[vrD].w[i] = (res < gCPU.vr[vrA].w[i]) ? 1 : 0;
	}
}

/*	vaddubs		Vector Add Unsigned Byte Saturate
 *	v.142
 */
void ppc_opc_vaddubs()
{
	VECTOR_DEBUG;
	int vrD, vrA, vrB;
	uint16 res;
	PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB);
	int i;
	for (i=0; i<16; i++) {
		res = (uint16)gCPU.vr[vrA].b[i] + (uint16)gCPU.vr[vrB].b[i];
		gCPU.vr[vrD].b[i] = SATURATE_UB(res);
	}
}

/*	vaddsbs		Vector Add Signed Byte Saturate
 *	v.138
 */
void ppc_opc_vaddsbs()
{
	VECTOR_DEBUG;
	int vrD, vrA, vrB;
	sint16 res;
	PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB);
	int i;
	for (i=0; i<16; i++) {
		res = (sint16)gCPU.vr[vrA].sb[i] + (sint16)gCPU.vr[vrB].sb[i];
		gCPU.vr[vrD].b[i] = SATURATE_SB(res);
	}
}

/*	vadduhs		Vector Add Unsigned Half Word Saturate
 *	v.144
 */
void ppc_opc_vadduhs()
{
	VECTOR_DEBUG;
	int vrD, vrA, vrB;
	uint32 res;
	PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB);
	int i;
	for (i=0; i<8; i++) {
		res = (uint32)gCPU.vr[vrA].h[i] + (uint32)gCPU.vr[vrB].h[i];
		gCPU.vr[vrD].h[i] = SATURATE_UH(res);
	}
}

/*	vaddshs		Vector Add Signed Half Word Saturate
 *	v.139
 */
void ppc_opc_vaddshs()
{
	VECTOR_DEBUG;
	int vrD, vrA, vrB;
	sint32 res;
	PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB);
	int i;
	for (i=0; i<8; i++) {
		res = (sint32)gCPU.vr[vrA].sh[i] + (sint32)gCPU.vr[vrB].sh[i];
		gCPU.vr[vrD].h[i] = SATURATE_SH(res);
	}
}

/*	vadduws		Vector Add Unsigned Word Saturate
 *	v.146
 */
void ppc_opc_vadduws()
{
	VECTOR_DEBUG;
	int vrD, vrA, vrB;
	uint32 res;
	PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB);
	int i;
	for (i=0; i<4; i++) {
		res = gCPU.vr[vrA].w[i] + gCPU.vr[vrB].w[i];

		// We do this to prevent us from having to do 64-bit math
		if (res < gCPU.vr[vrA].w[i]) {
			res = 0xFFFFFFFF;
			gCPU.vscr |= VSCR_SAT;
		}

	/*	64-bit math		|	32-bit hack
	 *	------------------------+-------------------------------------
	 *	add, addc	(a+b)	|	add		(a+b)
	 *	sub, subb 	(r>ub)	|	sub		(r<a)
	 */

		gCPU.vr[vrD].w[i] = res;
	}
}

/*	vaddsws		Vector Add Signed Word Saturate
 *	v.140
 */
void ppc_opc_vaddsws()
{
	VECTOR_DEBUG;
	int vrD, vrA, vrB;
	uint32 res;
	PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB);
	int i;
	for (i=0; i<4; i++) {
		res = gCPU.vr[vrA].w[i] + gCPU.vr[vrB].w[i];

		// We do this to prevent us from having to do 64-bit math
		if (((gCPU.vr[vrA].w[i] ^ gCPU.vr[vrB].w[i]) & SIGN32) == 0) {
			// the signs of both operands are the same

			if (((res ^ gCPU.vr[vrA].w[i]) & SIGN32) != 0) {
				// sign of result != sign of operands

				// if res is negative, should have been positive
				res = (res & SIGN32) ? (SIGN32 - 1) : SIGN32;
				gCPU.vscr |= VSCR_SAT;
			}
		}

	/*	64-bit math		|	32-bit hack
	 *	------------------------+-------------------------------------
	 *	add, addc	(a+b)	|	add		(a+b)
	 *	sub, subb 	(r>ub)	|	xor, and	(sign == sign)
	 *	sub, subb	(r<lb)	|	xor, and	(sign != sign)
	 *				|	and		(which)
	 */

		gCPU.vr[vrD].w[i] = res;
	}
}

/*	vsububm		Vector Subtract Unsigned Byte Modulo
 *	v.265
 */
void ppc_opc_vsububm()
{
	VECTOR_DEBUG;
	int vrD, vrA, vrB;
	uint8 res;
	PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB);
	int i;
	for (i=0; i<16; i++) {
		res = gCPU.vr[vrA].b[i] - gCPU.vr[vrB].b[i];
		gCPU.vr[vrD].b[i] = res;
	}
}

/*	vsubuhm		Vector Subtract Unsigned Half Word Modulo
 *	v.267
 */
void ppc_opc_vsubuhm()
{
	VECTOR_DEBUG;
	int vrD, vrA, vrB;
	uint16 res;
	PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB);
	int i;
	for (i=0; i<8; i++) {
		res = gCPU.vr[vrA].h[i] - gCPU.vr[vrB].h[i];
		gCPU.vr[vrD].h[i] = res;
	}
}

/*	vsubuwm		Vector Subtract Unsigned Word Modulo
 *	v.269
 */
void ppc_opc_vsubuwm()
{
	VECTOR_DEBUG;
	int vrD, vrA, vrB;
	uint32 res;
	PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB);
	int i;
	for (i=0; i<4; i++) {
		res = gCPU.vr[vrA].w[i] - gCPU.vr[vrB].w[i];
		gCPU.vr[vrD].w[i] = res;
	}
}

/*	vsubfp		Vector Subtract Float Point
 *	v.261
 */
void ppc_opc_vsubfp()
{
	VECTOR_DEBUG;
	int vrD, vrA, vrB;
	float res;
	PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB);
	int i;
	for (i=0; i<4; i++) { //FIXME: This might not comply with Java FP
		res = gCPU.vr[vrA].f[i] - gCPU.vr[vrB].f[i];
		gCPU.vr[vrD].f[i] = res;
	}
}

/*	vsubcuw		Vector Subtract Carryout Unsigned Word
 *	v.260
 */
void ppc_opc_vsubcuw()
{
	VECTOR_DEBUG;
	int vrD, vrA, vrB;
	uint32 res;
	PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB);
	int i;
	for (i=0; i<4; i++) {
		res = gCPU.vr[vrA].w[i] - gCPU.vr[vrB].w[i];
		gCPU.vr[vrD].w[i] = (res <= gCPU.vr[vrA].w[i]) ? 1 : 0;
	}
}

/*	vsububs		Vector Subtract Unsigned Byte Saturate
 *	v.266
 */
void ppc_opc_vsububs()
{
	VECTOR_DEBUG;
	int vrD, vrA, vrB;
	uint16 res;
	PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB);
	int i;
	for (i=0; i<16; i++) {
		res = (uint16)gCPU.vr[vrA].b[i] - (uint16)gCPU.vr[vrB].b[i];

		gCPU.vr[vrD].b[i] = SATURATE_0B(res);
	}
}

/*	vsubsbs		Vector Subtract Signed Byte Saturate
 *	v.262
 */
void ppc_opc_vsubsbs()
{
	VECTOR_DEBUG;
	int vrD, vrA, vrB;
	sint16 res;
	PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB);
	int i;
	for (i=0; i<16; i++) {
		res = (sint16)gCPU.vr[vrA].sb[i] - (sint16)gCPU.vr[vrB].sb[i];

		gCPU.vr[vrD].sb[i] = SATURATE_SB(res);
	}
}

/*	vsubuhs		Vector Subtract Unsigned Half Word Saturate
 *	v.268
 */
void ppc_opc_vsubuhs()
{
	VECTOR_DEBUG;
	int vrD, vrA, vrB;
	uint32 res;
	PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB);
	int i;
	for (i=0; i<8; i++) {
		res = (uint32)gCPU.vr[vrA].h[i] - (uint32)gCPU.vr[vrB].h[i];

		gCPU.vr[vrD].h[i] = SATURATE_0H(res);
	}
}

/*	vsubshs		Vector Subtract Signed Half Word Saturate
 *	v.263
 */
void ppc_opc_vsubshs()
{
	VECTOR_DEBUG;
	int vrD, vrA, vrB;
	sint32 res;
	PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB);
	int i;
	for (i=0; i<8; i++) {
		res = (sint32)gCPU.vr[vrA].sh[i] - (sint32)gCPU.vr[vrB].sh[i];

		gCPU.vr[vrD].sh[i] = SATURATE_SH(res);
	}
}

/*	vsubuws		Vector Subtract Unsigned Word Saturate
 *	v.270
 */
void ppc_opc_vsubuws()
{
	VECTOR_DEBUG;
	int vrD, vrA, vrB;
	uint32 res;
	PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB);
	int i;
	for (i=0; i<4; i++) {
		res = gCPU.vr[vrA].w[i] - gCPU.vr[vrB].w[i];

		// We do this to prevent us from having to do 64-bit math
		if (res > gCPU.vr[vrA].w[i]) {
			res = 0;
			gCPU.vscr |= VSCR_SAT;
		}

	/*	64-bit math		|	32-bit hack
	 *	------------------------+-------------------------------------
	 *	sub, subb	(a+b)	|	sub		(a+b)
	 *	sub, subb 	(r>ub)	|	sub		(r<a)
	 */

		gCPU.vr[vrD].w[i] = res;
	}
}

/*	vsubsws		Vector Subtract Signed Word Saturate
 *	v.264
 */
void ppc_opc_vsubsws()
{
	VECTOR_DEBUG;
	int vrD, vrA, vrB;
	uint32 res, tmp;
	PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB);
	int i;
	for (i=0; i<4; i++) {
		tmp = -gCPU.vr[vrB].w[i];
		res = gCPU.vr[vrA].w[i] + tmp;

		// We do this to prevent us from having to do 64-bit math
		if (((gCPU.vr[vrA].w[i] ^ tmp) & SIGN32) == 0) {
			// the signs of both operands are the same

			if (((res ^ tmp) & SIGN32) != 0) {
				// sign of result != sign of operands

				// if res is negative, should have been positive
				res = (res & SIGN32) ? (SIGN32 - 1) : SIGN32;
				gCPU.vscr |= VSCR_SAT;
			}
		}

	/*	64-bit math		|	32-bit hack
	 *	------------------------+-------------------------------------
	 *	sub, subc	(a+b)	|	neg, add	(a-b)
	 *	sub, subb 	(r>ub)	|	xor, and	(sign == sign)
	 *	sub, subb	(r<lb)	|	xor, and	(sign != sign)
	 *				|	and		(which)
	 */

		gCPU.vr[vrD].w[i] = res;
	}
}

/*	vmuleub		Vector Multiply Even Unsigned Byte
 *	v.209
 */
void ppc_opc_vmuleub()
{
	VECTOR_DEBUG;
	int vrD, vrA, vrB;
	uint16 res;
	PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB);
	int i;
	for (i=0; i<8; i++) {
		res = (uint16)gCPU.vr[vrA].b[VECT_EVEN(i)] *
			 (uint16)gCPU.vr[vrB].b[VECT_EVEN(i)];

		gCPU.vr[vrD].h[i] = res;
	}
}

/*	vmulesb		Vector Multiply Even Signed Byte
 *	v.207
 */
void ppc_opc_vmulesb()
{
	VECTOR_DEBUG;
	int vrD, vrA, vrB;
	sint16 res;
	PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB);
	int i;
	for ( i=0; i<8; i++) {
		res = (sint16)gCPU.vr[vrA].sb[VECT_EVEN(i)] *
			 (sint16)gCPU.vr[vrB].sb[VECT_EVEN(i)];

		gCPU.vr[vrD].sh[i] = res;
	}
}

/*	vmuleuh		Vector Multiply Even Unsigned Half Word
 *	v.210
 */
void ppc_opc_vmuleuh()
{
	VECTOR_DEBUG;
	int vrD, vrA, vrB;
	uint32 res;
	PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB);
	int i;
	for (i=0; i<4; i++) {
		res = (uint32)gCPU.vr[vrA].h[VECT_EVEN(i)] *
			 (uint32)gCPU.vr[vrB].h[VECT_EVEN(i)];

		gCPU.vr[vrD].w[i] = res;
	}
}

/*	vmulesh		Vector Multiply Even Signed Half Word
 *	v.208
 */
void ppc_opc_vmulesh()
{
	VECTOR_DEBUG;
	int vrD, vrA, vrB;
	sint32 res;
	PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB);
	int i;
	for (i=0; i<4; i++) {
		res = (sint32)gCPU.vr[vrA].sh[VECT_EVEN(i)] *
			 (sint32)gCPU.vr[vrB].sh[VECT_EVEN(i)];

		gCPU.vr[vrD].sw[i] = res;
	}
}

/*	vmuloub		Vector Multiply Odd Unsigned Byte
 *	v.213
 */
void ppc_opc_vmuloub()
{
	VECTOR_DEBUG;
	int vrD, vrA, vrB;
	uint16 res;
	PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB);
	int i;
	for (i=0; i<8; i++) {
		res = (uint16)gCPU.vr[vrA].b[VECT_ODD(i)] *
			 (uint16)gCPU.vr[vrB].b[VECT_ODD(i)];

		gCPU.vr[vrD].h[i] = res;
	}
}

/*	vmulosb		Vector Multiply Odd Signed Byte
 *	v.211
 */
void ppc_opc_vmulosb()
{
	VECTOR_DEBUG;
	int vrD, vrA, vrB;
	sint16 res;
	PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB);
	int i;
	for (i=0; i<8; i++) {
		res = (sint16)gCPU.vr[vrA].sb[VECT_ODD(i)] *
			 (sint16)gCPU.vr[vrB].sb[VECT_ODD(i)];

		gCPU.vr[vrD].sh[i] = res;
	}
}

/*	vmulouh		Vector Multiply Odd Unsigned Half Word
 *	v.214
 */
void ppc_opc_vmulouh()
{
	VECTOR_DEBUG;
	int vrD, vrA, vrB;
	uint32 res;
	PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB);
	int i;
	for (i=0; i<4; i++) {
		res = (uint32)gCPU.vr[vrA].h[VECT_ODD(i)] *
			 (uint32)gCPU.vr[vrB].h[VECT_ODD(i)];

		gCPU.vr[vrD].w[i] = res;
	}
}

/*	vmulosh		Vector Multiply Odd Signed Half Word
 *	v.212
 */
void ppc_opc_vmulosh()
{
	VECTOR_DEBUG;
	int vrD, vrA, vrB;
	sint32 res;
	PPC_OPC_TEMPL_X(gCPU.current_opc, vrD, vrA, vrB);
	int i;
	for (i=0; i<4; i++) {
		res = (sint32)gCPU.vr[vrA].sh[VECT_ODD(i)] *
			 (sint32)gCPU.vr[vrB].sh[VECT_ODD(i)];

		gCPU.vr[vrD].sw[i] = res;
	}
}

/*	vmaddfp		Vector Multiply Add Floating Point
 *	v.177
 */
void ppc_opc_vmaddfp()
{
	VECTOR_DEBUG;
	int vrD, vrA, vrB, vrC;
	double res;
	PPC_OPC_TEMPL_A(gCPU.current_opc, vrD, vrA, vrB, vrC);
	int i;
	for (i=0; i<4; i++) { //FIXME: This might not comply with Java FP
		res = (double)gCPU.vr[vrA].f[i] * (double)gCPU.vr[vrC].f[i];

		res = (double)gCPU.vr[vrB].f[i] + res;

		gCPU.vr[vrD].f[i] = (float)res;
	}
}

/*	vmhaddshs	Vector Multiply High and Add Signed Half Word Saturate
 *	v.185
 */
void ppc_opc_vmhaddshs()
{
	VECTOR_DEBUG;
	int vrD, vrA, vrB, vrC;
	sint32 prod;
	PPC_OPC_TEMPL_A(gCPU.current_opc, vrD, vrA, vrB, vrC);
	int i;
	for (i=0; i<8; i++) {
		prod = (sint32)gCPU.vr[vrA].sh[i] * (sint32)gCPU.vr[vrB].sh[i];

		prod = (prod >> 15) + (sint32)gCPU.vr[vrC].sh[i];

		gCPU.vr[vrD].sh[i] = SATURATE_SH(prod);
	}
}

/*	vmladduhm	Vector Multiply Low and Add Unsigned Half Word Modulo
 *	v.194
 */
void ppc_opc_vmladduhm()
{
	VECTOR_DEBUG;
	int vrD, vrA, vrB, vrC;