📄 skyeye_mach_mcf5272.c
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continue; } icr_level = ICR_LEVEL(x); if(icr_level != interrupt_level) continue; /* see p163 of user manual of 5272 */ vector = (32 - x) | (io->pivr & 0xe0); /* if(x != 24) printf("DBG: in %s, vector=%d\n", __FUNCTION__, vector); */ return vector; } //ERR("Inside iack_func, but no interrupt is waiting with level %d\n", interrupt_level); fprintf(stderr, "Inside iack_func, but no interrupt is waiting with level %d\n", interrupt_level); return 0;}static void interrupt_assert(short number){ mcf5272_io_t * io = &mcf5272_io; int level = ICR_LEVEL(number);; /* if(number != 24) printf("DBG:Posting interrupt Number=%d, Level=%d\n", number, level); */ //TRACE("Posting interrupt Number=%d, Vector=%d\n", number, vector); /* Post an interrupt */ exception_post(level, &mcf5272_iack_func); io->isr |= 0x1 << number; return;}static void interrupt_withdraw(short number){ mcf5272_io_t * io = &mcf5272_io; int icr_level = ICR_LEVEL(number); io->isr &= ~(0x1 << number); /* if(number != 24) printf("DBG:in %s Number=%d, Level=%d\n", __FUNCTION__, number, icr_level); */ exception_withdraw(icr_level); //TRACE("Done.\n"); return;}void mcf5272_io_do_cycle(){ int i; for(i = 0; i < TIMER_NUM; i++){ //mcf5272_timer_t * timer = &mcf5272_io.timer[i]; /* check if timer is enbaled */ if(mcf5272_io.timer[i].tmr & 0x1){ mcf5272_io.timer[i].tcn++; /* check if reference interrupt is enabled */ if((mcf5272_io.timer[i].tcn == mcf5272_io.timer[i].trr) && (mcf5272_io.timer[i].tmr & 0x10)) { //printf("DBG:tcn=0x%x,trr=0x%x,i=%d\n", mcf5272_io.timer[i].tcn, mcf5272_io.timer[i].trr, i); /* set REF bit in TER */ mcf5272_io.timer[i].ter |= 0x2; interrupt_assert(TIMER0_IRQ - i); /* check if in restart mode */ if(mcf5272_io.timer[i].tmr & 0x8) mcf5272_io.timer[i].tcn = 0x0; } } } if(1){ /* UART FIFO full interrupt enabled */ struct timeval tv; unsigned char buf; tv.tv_sec = 0; tv.tv_usec = 0; if(skyeye_uart_read(-1, &buf, 1, &tv, NULL) > 0){ mcf5272_io.uart[0].urb = buf; /* set RXRDY bit in UISR */ mcf5272_io.uart[0].uisr |= 0x2; } /* set TXRDY bit in UISR */ mcf5272_io.uart[0].uisr |= 0x1; } /* check if UART Transmitter ready interrupt enabled */ if(!(mcf5272_io.isr & UART1_IRQ)){ if((mcf5272_io.uart[0].uimr & mcf5272_io.uart[0].uisr)) interrupt_assert(UART1_IRQ); }}static char cs_module_read(unsigned int *result, short size, int offset){ int index = offset - 0x80; int reg_no; if(index >= 0 && index <=8){ reg_no = index / 4; index = 0; } if(index >= 0xc && index <= 0x16){ reg_no = (index - 0xc)/ 4; index = 1; } if(index >= 0x18 && index <= 0x22){ reg_no = (index - 0x18)/4; index = 2; } if(index >= 0x24 && index <= 0x2e){ reg_no = (index - 0x24); index = 3; } switch(reg_no){/* case CSAR: *result = mcf5272_io.cs_module[index].csar; return 1; case CSMR: *result = mcf5272_io.cs_module[index].csmr; return 1; case CSCR: *result = mcf5272_io.cs_module[index].cscr; return 1;*/ default: fprintf(stderr,"Error adress in %s,offset=0x%x\n",__FUNCTION__,offset); skyeye_exit(-1); return 0; }}static char cs_module_write(short size, int offset, unsigned int value){ int index = offset - 0x80; int reg_no; if(index >= 0 && index <=8){ reg_no = index / 4; index = 0; } if(index >= 0xc && index <= 0x16){ reg_no = (index - 0xc)/ 4; index = 1; } if(index >= 0x18 && index <= 0x22){ reg_no = (index - 0x18)/4; index = 2; } if(index >= 0x24 && index <= 0x2e){ reg_no = (index - 0x24); index = 3; } switch(reg_no){/* case CSAR: mcf5272_io.cs_module[index].csar = value; return 1; case CSMR: mcf5272_io.cs_module[index].csmr = value; return 1; case CSCR: mcf5272_io.cs_module[index].cscr = value; return 1;*/ default: fprintf(stderr,"Error adress in %s,offset=0x%x\n",__FUNCTION__,offset); skyeye_exit(-1); return 0; }}static char timer_read(unsigned int *result, short size, int offset){ int index = (offset - 0x200) / 0x20; offset = offset % 0x20; //printf("DBG: in %s, offset = 0x%x", __FUNCTION__, offset); switch(offset){ case 0x0: *result = mcf5272_io.timer[index].tmr; return 1; case 0x4: *result = mcf5272_io.timer[index].trr; return 1; case 0x8: *result = mcf5272_io.timer[index].tcap; return 1; case 0xc: *result = mcf5272_io.timer[index].tcn; return 1; case 0x11: /* write one to clear the corresponding bit */ *result = mcf5272_io.timer[index].ter; /* clear the corresponding bit in ipr */ //mcf5272_io.ipr &= ~(0x1 << 9); interrupt_withdraw(TIMER0_IRQ - index); return 1; default: fprintf(stderr,"Error adress in %s,offset=0x%x\n",__FUNCTION__,offset); skyeye_exit(-1); return 0; }}static char timer_write(short size, int offset, unsigned int value){ printf("DBG: in %s, offset = 0x%x, value=0x%x\n", __FUNCTION__, offset, value); int index = (offset - 0x200) / 0x20; offset = offset % 0x20; switch(offset){ case 0x0: mcf5272_io.timer[index].tmr = value; return 1; case 0x4: mcf5272_io.timer[index].trr = value; return 1; case 0x8: mcf5272_io.timer[index].tcap = value; return 1; case MCFTIMER_TCN: mcf5272_io.timer[index].tcn = value; return 1; case MCFTIMER_TER: /* write one to clear the corresponding bit */ mcf5272_io.timer[index].ter &= ~(value & 0x3); /* clear the corresponding bit in ipr */ //mcf5272_io.ipr &= ~(0x1 << 9); interrupt_withdraw(TIMER0_IRQ - index); return 1; default: fprintf(stderr,"Error adress in %s,offset=0x%x\n",__FUNCTION__,offset); //skyeye_exit(-1); return 0; }}static char uart_read(unsigned int *result, short size, int offset){ int index; if(offset >= 0x100 && offset <= 0x13C){ index = 0; offset = offset - 0x100; } if(offset >= 0x140 && offset <= 0x17C){ index = 1; offset = offset - 0x140; } extern struct _memory_core memory_core; /* if(offset != 0x4) printf("DBG: in %s, offset = 0x%x,PC=0x%x\n", __FUNCTION__, offset, memory_core.pc); */ switch(offset){ case 0x0: *result = mcf5272_io.uart[index].umr1; break; case 0x4: *result = mcf5272_io.uart[index].usr; break; case 0xC: *result = mcf5272_io.uart[index].urb; /* set FFULL bit in USR is zero */ mcf5272_io.uart[index].usr &= ~0x2; /* set RxRDY bit in USR is zero */ mcf5272_io.uart[index].usr &= ~0x1; /* check RXIRQ bit in UMR1 */ //if(mcf5272_io.uart[index].umr1 & 0x40) mcf5272_io.uart[index].uisr &= ~0x2; break; case 0x10: *result = mcf5272_io.uart[index].uipcr; break; case 0x14: *result = mcf5272_io.uart[index].uisr; mcf5272_io.uart[index].uisr = 0x0; interrupt_withdraw(UART1_IRQ - index); break; case 0x18: *result = mcf5272_io.uart[index].ubg1; break; case 0x1C: *result = mcf5272_io.uart[index].ubg2; break; case 0x34: *result = mcf5272_io.uart[index].uip; break; default: fprintf(stderr,"Error adress in %s,offset=0x%x\n",__FUNCTION__,offset); skyeye_exit(-1); return 0; } return 1;}static char uart_write(short size, int offset, unsigned int value){ int index, cmd; char tmp; if(offset >= 0x100 && offset <= 0x13C){ index = 0; offset = offset - 0x100; } if(offset >= 0x140 && offset <= 0x17C){ index = 1; offset = offset - 0x140; } /* if(offset != 0xc) printf("DBG: in %s, offset = 0x%x, value=0x%x\n", __FUNCTION__, offset, value); */ switch(offset){ case 0x0: mcf5272_io.uart[index].umr1 = value; break; case 0x4: mcf5272_io.uart[index].ucsr = value; break; case 0x8: mcf5272_io.uart[index].ucr = value; if((value & 0x3) == 0x1) /* Receiver enable */ ; if(((value >> 2) & 0x3) == 0x1) /* Transmitter enable */ /* set TXRDY bit and TXEMP bit in usr */ mcf5272_io.uart[index].usr |= 0xc; cmd = (value >> 4) & 0x7; if (cmd == 0x4) /* Reset error status */ mcf5272_io.uart[index].usr &= 0xf; break; case 0xc: mcf5272_io.uart[index].utb = value; tmp = value & 0xff; skyeye_uart_write(-1, &tmp, 1, NULL); /* set TXRDY bit and TXEMP bit in usr */ mcf5272_io.uart[index].usr |= 0xc; /* set TXRDY bit in usr */ mcf5272_io.uart[index].uisr |= 0x1; break; case 0x10: mcf5272_io.uart[index].uacr = value; break; case 0x14: mcf5272_io.uart[index].uimr = value; break; case 0x18: mcf5272_io.uart[index].ubg1 = value; break; case 0x1C: mcf5272_io.uart[index].ubg2 = value; break; case 0x30: mcf5272_io.uart[index].ufpd = value; break; case 0x38: mcf5272_io.uart[index].uop1 = value; break; case 0x3C: mcf5272_io.uart[index].uop0 = value; break; default: fprintf(stderr,"Error adress in %s,offset=0x%x\n",__FUNCTION__,offset); skyeye_exit(-1); return 0; } return 1;}void mcf5272_mach_init(void * state, machine_config_t * mach){ struct _memory_core * core = (struct _memory_core *)state; machine_config_t * this_mach = mach; core->mbar_read = mcf5272_mbar_read; core->mbar_write = mcf5272_mbar_write; core->mbar2_read = mcf5272_mbar2_read; core->mbar2_write = mcf5272_mbar2_write; mcf5272_io.uart[0].usr |= 0xc; /* init io value */ /* fixme, workaround for uClinux */ mcf5272_io.pivr = 0x40; /* init mach */ if (!this_mach) { exit (-1); } this_mach->mach_io_do_cycle = mcf5272_io_do_cycle;#if 0 this_mach->mach_io_read_byte = mcf5272_io_read_byte; this_mach->mach_io_read_halfword = mcf5272_io_read_halfword; this_mach->mach_io_read_word = mcf5272_io_read_word; this_mach->mach_io_write_byte = mcf5272_io_write_byte; this_mach->mach_io_write_halfword = mcf5272_io_write_halfword; this_mach->mach_io_write_word = mcf5272_io_write_word; this_mach->mach_io_do_cycle = mcf5272_io_do_cycle; this_mach->mach_set_intr = mcf5272_set_int;#endif}
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