bf533_io.c

SkyEye是一个可以运行嵌入式操作系统的硬件仿真工具

		io.core_int.ipend = v;
		break;
	case 0x10c:
		io.core_int.ilat = v;
		//printf("write ilat %x\n",v);
		break;
	case 0x110:
		io.core_int.iprio = v;
		break;
	default:
		if (offset >= 0 && offset < 0x100) {
			io.core_int.evt[offset >> 2] = v;
			return;
		}
		IO_ERR;
	}
}
static bu32
core_int_read_long (bu32 addr)
{
	int offset = addr - CORE_INT_IO_START_ADDR;
	bu32 ret;
	//printf("read %x\n",offset);
	switch (offset) {
	case 0x104:
		ret = (io.core_int.imask | 0x1f) & 0xffff;
		break;
	case 0x108:
		ret = io.core_int.ipend;
		break;
	case 0x10c:
		ret = io.core_int.ilat;
		//printf("read ilat %x",ret);
		break;
	case 0x110:
		ret = io.core_int.iprio;
		break;
	default:
		if (offset >= 0 && offset < 0x100) {
			ret = io.core_int.evt[offset >> 2];
			return ret;
		}
		IO_ERR;

	}
	return ret;

}
static void
wd_write_word (bu32 addr, bu16 v)
{
	int offset = addr - WD_IO_START_ADDR;
	switch (offset) {
	case 0x0:
		io.wd.ctl = v;
		break;
	case 0x4:
		io.wd.cnt = v;
		break;
	case 0x8:
		io.wd.stat = v;
		break;
	default:
		IO_ERR;
	}
}



static bu32
deu_read_long (bu32 addr)
{
	int offset = addr - DEU_IO_START_ADDR;
	switch (offset) {
	case 0x0:
		return io.deu.dspid;
	default:
		IO_ERR;

	}
}

static bu16
dpmc_read_word (bu32 addr)
{
	int offset = addr - DPMC_IO_START_ADDR;
	bu16 ret;
	switch (offset) {
	case 0x0:
		ret = io.dpmc.pll_ctl;
		break;
	case 0x4:
		ret = io.dpmc.pll_div;
		break;
	case 0x8:
		ret = io.dpmc.vr_ctl;
		break;
	case 0xc:
		ret = io.dpmc.pll_stat;	/*PLL_LOCKED is set */
		break;
	case 0x10:
		ret = io.dpmc.pll_lockcnt;
		break;
	default:
		IO_ERR;
	}
	return ret;
}
static void
dpmc_write_word (bu32 addr, bu16 v)
{
	int offset = addr - DPMC_IO_START_ADDR;
	switch (offset) {
	case 0x0:
		io.dpmc.pll_ctl = v;
		break;
	case 0x4:
		io.dpmc.pll_div = v;
		break;
	case 0x8:
		io.dpmc.vr_ctl = v;
		break;
	case 0xc:
		io.dpmc.pll_stat = v;
		break;
	case 0x10:
		io.dpmc.pll_lockcnt = v;
		break;
	default:
		IO_ERR;
	}
	return;
}
static bu32
tbuf_read_long (bu32 addr)
{
	int offset = addr - TBUF_IO_START_ADDR;
	switch (offset) {
	case 0:
		return io.tbuf.ctrl;
	case 4:
		return io.tbuf.stat;

	case 0x100:
	  if (io.tbuf.rsel == 1) {
	        io.tbuf.rsel = 0;
	        if (io.tbuf.rix >= 16) io.tbuf.rix = 0;
		return io.tbuf.sbuf[io.tbuf.rix];
	  } else {
	        io.tbuf.rsel = 1;
		return io.tbuf.dbuf[io.tbuf.rix++];
	  }
	  break;

	default:
		IO_ERR;
 	        break;

	}
	return 0;

}
static void
tbuf_write_long (bu32 addr, bu32 v)
{
	int offset = addr - TBUF_IO_START_ADDR;
	switch (offset) {
	case 0:
		io.tbuf.ctrl = v;
		break;
	case 4:
		io.tbuf.stat = v;
		break;

	case 0x100:
	  if (io.tbuf.wsel == 1) {
	        io.tbuf.wsel = 0;
	        if (io.tbuf.wix >= 16) io.tbuf.wix = 0;
		io.tbuf.sbuf[io.tbuf.wix] = v;
	  } else {
	        io.tbuf.wsel = 1;
		io.tbuf.dbuf[io.tbuf.wix++] = v;
	  }
	  break;

	default:
		IO_ERR;
 	        break;

	}
	return ;
}


static bu32
sic_read_long (bu32 addr)
{
	int offset = addr - SIC_IO_START_ADDR;
	bu32 ret;
	switch (offset) {
	case 0x0:
		ret = io.sic.swrst;
		break;
	case 0x4:
		ret = io.sic.syscr;
		break;
	case 0xc:
		ret = io.sic.sic_imask;
		//printf("read ret= %x\n",ret);
		break;
	case 0x20:
		ret = io.sic.sic_isr;
		//printf("read sic_isr 0x%x\n",ret);
		break;
	case 0x24:
		ret = io.sic.sic_iwr;
		break;
	default:
		if (offset >= 0x10 && offset <= 0x18) {
			ret = io.sic.sic_iar[(offset - 0x10) >> 2];
			return ret;
		}

		IO_ERR;
	}
	return ret;
}
static void
sic_write_long (bu32 addr, bu32 v)
{
	int offset = addr - SIC_IO_START_ADDR;
	switch (offset) {
	case 0x24:
		io.sic.sic_iwr = v;
		break;
	case 0xc:
		//printf("write v=%x\n",v);
		io.sic.sic_imask = v;
		break;

	default:
		if (offset >= 0x10 && offset <= 0x18) {
			io.sic.sic_iar[(offset - 0x10) >> 2] = v;
			return;
		}
		IO_ERR;
	}
}
static void
l1mem_write_long (bu32 addr, bu32 v)
{
	int offset = addr - L1MEM_IO_START_ADDR;
	int pos = offset >> 2;
	switch (pos) {
	default:
		io.l1mem.reg[pos] = v;
		break;
	}
}
static bu32
l1mem_read_long (bu32 addr)
{
	int offset = addr - L1MEM_IO_START_ADDR;
	int pos = offset >> 2;
	bu32 ret;
	switch (pos) {
	default:
		ret = io.l1mem.reg[pos];
	}
	return ret;
}
static void
l1dmem_write_long (bu32 addr, bu32 v)
{
	int offset = addr - L1DMEM_IO_START_ADDR;
	int pos = offset >> 2;
	switch (pos) {
	default:
		io.l1dmem.reg[pos];
		break;
	}
}
static void
rtc_write_word (bu32 addr, bu16 v)
{
	int offset = addr - RTC_IO_START_ADDR;
	switch (offset) {
	case 0x4:
		io.rtc.ictl = v;
		return;
	case 0x14:
		io.rtc.pren = v;
		/*set write complete bit to one */
		io.rtc.istat |= 0x8000;
		return;
	case 0x8:
		io.rtc.istat = v;
		return;

	default:
		IO_ERR;
	}
}
static bu16
rtc_read_word (bu32 addr)
{
	int offset = addr - RTC_IO_START_ADDR;
	bu16 ret;
	switch (offset) {

	case 0x14:
		ret = io.rtc.pren;
		break;
	case 0x8:
		ret = io.rtc.istat;
		/*clear write complete bit */
		io.rtc.istat &= ~0x8000;
		break;
	default:
		IO_ERR;
	}
	return ret;

}
static void
rtc_write_long (bu32 addr, bu32 v)
{
	int offset = addr - RTC_IO_START_ADDR;
	switch (offset) {
	case 0x0:
		io.rtc.stat = v;
		return;
	case 0x10:
		io.rtc.alarm = v;
		return;
	default:
		IO_ERR;
	}
}
static bu32
rtc_read_long (bu32 addr)
{
	int offset = addr - RTC_IO_START_ADDR;
	bu32 ret;
	switch (offset) {
	case 0x0:
		ret = io.rtc.stat;
		break;
	default:
		IO_ERR;
	}
	return ret;
}
static bu32
l1dmem_read_long (bu32 addr)
{
	int offset = addr - L1DMEM_IO_START_ADDR;
	int pos = offset >> 2;
	bu32 ret;
	switch (pos) {
	default:
		ret = io.l1dmem.reg[pos];
		break;
	}
	return ret;
}
static void
core_timer_write_long (bu32 addr, bu32 v)
{
	int offset = addr - CORE_TIMER_IO_START_ADDR;
	//printf("offset=%x",offset);
	switch (offset) {
	case 0x0:
		io.core_timer.tcntl = v;
		/*not sure core_int is open at this time */
		if (io.core_timer.tcntl & 0x2) {
			io.core_int.imask |= 1 << CORE_TIMER_IRQ;
		}
                /* if autorld is enabled reload tcount */
                if (io.core_timer.tcntl & 0x4) {
                     io.core_timer.tcount = io.core_timer.tperiod / 10;
                }
		break;
	case 0x4:
		io.core_timer.tperiod = v;
		break;
	case 0x8:
		io.core_timer.tscale = v;
		break;
	case 0xc:
		io.core_timer.tcount = v;
		break;
	default:
		IO_ERR;
	}
	return;
}
static bu32
core_timer_read_long (bu32 addr)
{
	int offset = addr - CORE_TIMER_IO_START_ADDR;
	bu32 ret;
	switch (offset) {
	case 0x0:
		ret = io.core_timer.tcntl;
		break;
	case 0x4:
		ret = io.core_timer.tperiod;
		break;
	case 0x8:
		ret = io.core_timer.tscale;
		break;
	case 0xc:
		ret = io.core_timer.tcount;
		break;
	default:
		IO_ERR;
	}
	return ret;

}

static bu16
pf_read_word (bu32 addr)
{
	int offset = addr - PF_IO_START_ADDR;
	bu32 ret;
	switch (offset) {
	case 0x30:
		ret = io.pf.fio_dir;
		break;
	case 0x40:
		ret = io.pf.fio_inen;
		break;
	default:
		IO_ERR;
	}
	return ret;
}
static void
pf_write_word (bu32 addr, bu16 v)
{
	int offset = addr - PF_IO_START_ADDR;
	switch (offset) {
	case 0x4:
		io.pf.fio_flag_c = v;
		return;
	case 0x8:
		io.pf.fio_flag_s = v;
		return;
	case 0x14:
		io.pf.fio_maska_c = v;
		return;
	case 0x24:
		io.pf.fio_maskb_c = v;
		return;
	case 0x30:
		io.pf.fio_dir = v;
		return;
        case 0x10:  // Flag Mask Interrupt A Register (set directly)
        case 0x38:  // Flag Source Sensitivity Register
        case 0x40:  // Flag Input Enable Register
               return;

	default:
		IO_ERR;
	}
}

static void bf533_io_reset(){}

void
bf533_mach_init (void * curr_state, machine_config_t * this_mach)
{
	saved_state_type *p_state;

	/*init io  value */
	io.dpmc.pll_div = 0x0005;
	io.dpmc.pll_ctl = 0x1400;
	io.dpmc.pll_lockcnt = 0x0200;
	io.dpmc.pll_stat = 0x00a2;
	io.core_int.ipend = 0x10; /*at the beginning,global int is disabled*/
	io.core_int.imask = 0x1f;
	io.core_int.ilat = 0x0;
	/**/ 
        io.core_timer.tcntl   =  0;
        io.core_timer.tcount  =  BF533_HZ;
        io.core_timer.tperiod =  BF533_HZ;

	io.sic.sic_isr = 0x0;
	io.uart.lcr = 0x0;
	io.uart.dll = 0x0001;
	io.uart.ier = 0x0;
	io.uart.iir = 0x1;
	io.uart.lsr = 0x60;
        io.tbuf.ctrl = 0;
        io.tbuf.stat = 0;
        io.tbuf.rix = 0;
        io.tbuf.rsel = 0;
        io.tbuf.wix = 0;
        io.tbuf.wsel = 0;

	/*init mach */
	if (!this_mach) {
		skyeye_exit (-1);
	}
	this_mach->mach_io_read_byte = bf533_io_read_byte;
	this_mach->mach_io_read_halfword = bf533_io_read_word;
	this_mach->mach_io_read_word = bf533_io_read_long;
	this_mach->mach_io_write_byte = bf533_io_write_byte;
	this_mach->mach_io_write_halfword = bf533_io_write_word;
	this_mach->mach_io_write_word = bf533_io_write_long;
	this_mach->mach_io_do_cycle = bf533_io_do_cycle;
	this_mach->mach_io_reset = bf533_io_reset;
	this_mach->mach_set_intr = bf533_set_int;
	//this_mach->mach_update_intr = bf533_update_int;
	//this_mach->mach_pending_intr = bf533_pending_int;

	p_state = (saved_state_type *)curr_state;
	p_state->disable_int = bf533_disable_int;
	p_state->enable_int = bf533_enable_int;
	p_state->clear_int = bf533_clear_int;
	p_state->sti = bf533_sti;
	p_state->cli = bf533_cli;
	p_state->set_int = bf533_set_int;
}