bf533_io.c

SkyEye是一个可以运行嵌入式操作系统的硬件仿真工具

bf533_io_read_long (void * state, bu32 addr)
{
	switch (addr) {
	default:
		if (addr >= DMA_IO_START_ADDR && addr < DMA_IO_END_ADDR) {
			return dma_read_long (addr);
		}
		else if (addr >= UART_IO_START_ADDR
			 && addr < UART_IO_END_ADDR) {
			return uart_read_long (addr);
		}
		else if (addr >= DEU_IO_START_ADDR && addr < DEU_IO_END_ADDR) {
			return deu_read_long (addr);
		}
		else if (addr >= EBIU_IO_START_ADDR
			 && addr < EBIU_IO_END_ADDR) {
			return ebiu_read_long (addr);
		}
		else if (addr >= SIC_IO_START_ADDR && addr < SIC_IO_END_ADDR) {
			return sic_read_long (addr);
		}
		else if (addr >= L1MEM_IO_START_ADDR
			 && addr < L1MEM_IO_END_ADDR) {
			return l1mem_read_long (addr);
		}
		else if (addr >= L1DMEM_IO_START_ADDR
			 && addr < L1DMEM_IO_END_ADDR) {
			return l1dmem_read_long (addr);
		}
		else if (addr >= CORE_INT_IO_START_ADDR
			 && addr < CORE_INT_IO_END_ADDR) {
			return core_int_read_long (addr);
		}
		else if (addr >= RTC_IO_START_ADDR && addr < RTC_IO_END_ADDR) {
			return rtc_read_long (addr);
		}
		else if (addr >= CORE_TIMER_IO_START_ADDR
			 && addr < CORE_TIMER_IO_END_ADDR) {
			return core_timer_read_long (addr);
		}
		else if (addr >= TBUF_IO_START_ADDR
			 && addr < TBUF_IO_END_ADDR) {
			return tbuf_read_long (addr);
		}

		else {
			IO_ERR;
		}
	}

}
static void
bf533_io_write_byte (void * state, bu32 addr, bu8 v)
{
	switch (addr) {
	default:
		if (addr >= DMA_IO_START_ADDR && addr < DMA_IO_END_ADDR) {
			dma_write_byte (addr, v);

		}
		else if (addr >= UART_IO_START_ADDR
			 && addr < UART_IO_END_ADDR) {
			uart_write_byte (addr, v);
		}
		else {
			IO_ERR;
		}

	}
	return;
}

static void
bf533_io_write_word (void * state, bu32 addr, bu16 v)
{
	switch (addr) {
	default:
		if (addr >= DMA_IO_START_ADDR && addr < DMA_IO_END_ADDR) {
			dma_write_word (addr, v);

		}
		else if (addr >= UART_IO_START_ADDR
			 && addr < UART_IO_END_ADDR) {
			uart_write_word (addr, v);
		}
		else if (addr >= EBIU_IO_START_ADDR
			 && addr < EBIU_IO_END_ADDR) {
			ebiu_write_word (addr, v);
		}
		else if (addr >= WD_IO_START_ADDR && addr < WD_IO_END_ADDR) {
			wd_write_word (addr, v);
		}
		else if (addr >= DPMC_IO_START_ADDR
			 && addr < DPMC_IO_END_ADDR) {
			dpmc_write_word (addr, v);
		}
		else if (addr >= RTC_IO_START_ADDR && addr < RTC_IO_END_ADDR) {
			rtc_write_word (addr, v);
		}
		else if (addr >= PF_IO_START_ADDR && addr < PF_IO_END_ADDR) {
			pf_write_word (addr, v);
		}
		else {
			IO_ERR;
		}

	}
	return;
}
static void
bf533_io_write_long (void * state, bu32 addr, bu32 v)
{
	switch (addr) {
	default:
		if (addr >= DMA_IO_START_ADDR && addr < DMA_IO_END_ADDR) {
			dma_write_long (addr, v);

		}
		else if (addr >= UART_IO_START_ADDR
			 && addr < UART_IO_END_ADDR) {
			uart_write_long (addr, v);
		}
		else if (addr >= EBIU_IO_START_ADDR
			 && addr < EBIU_IO_END_ADDR) {
			ebiu_write_long (addr, v);
		}
		else if (addr >= CORE_INT_IO_START_ADDR
			 && addr < CORE_INT_IO_END_ADDR) {
			core_int_write_long (addr, v);
		}
		else if (addr >= SIC_IO_START_ADDR && addr < SIC_IO_END_ADDR) {
			sic_write_long (addr, v);
		}
		else if (addr >= L1MEM_IO_START_ADDR
			 && addr < L1MEM_IO_END_ADDR) {
			l1mem_write_long (addr, v);
		}
		else if (addr >= L1DMEM_IO_START_ADDR
			 && addr < L1DMEM_IO_END_ADDR) {
			l1dmem_write_long (addr, v);
		}
		else if (addr >= RTC_IO_START_ADDR && addr < RTC_IO_END_ADDR) {
			rtc_write_long (addr, v);
		}
		else if (addr >= CORE_TIMER_IO_START_ADDR
			 && addr < CORE_TIMER_IO_END_ADDR) {
			core_timer_write_long (addr, v);
		}
		else if (addr >= TBUF_IO_START_ADDR
			 && addr < TBUF_IO_END_ADDR) {
		  return tbuf_write_long (addr, v);
		}
		else {
			IO_ERR;
		}

	}
	return;
}

bu16
uart_read_word (bu32 addr)
{
	bu16 data;
	//printf("bf533_uart_read,addr=%x\n",addr);
	bu32 offset = addr - UART_IO_START_ADDR;
	/*
	   if(offset != 0 && offset != 0x14 && offset != 0xc && offset!=0x4)
	   printf("###############offset=0x%x\n",offset);
	 */
	static int read_num = 0;
	switch (offset) {
	case 0x0:		// RbR
		if (io.uart.lcr & 0x80) {
			data = io.uart.dlh;
		}

		if (read_num == 0) {
			read_num = 1;
			return 'k';
		}
		if (read_num == 1) {
			io.uart.lsr &= ~0x1;
			io.sic.sic_isr &= ~0x4000;
			data = io.uart.rbr & 0xff;
			//io.uart.iir = 0x1;
			read_num = 0;
			//fprintf (PF, "*****read rbr=%x,pc=%x,isr=%x\n", data,
			//	 PCREG, io.sic.sic_isr);
		}
		break;

	case 0x4:		// ier
		if (io.uart.lcr & 0x80)
			data = io.uart.dlh;
		else
			data = io.uart.ier;
		break;
	case 0x8:		// iir

		data = io.uart.iir;
		//printf("read iir=%x,pc=%x\n",data,PCREG);
		io.uart.iir = 0x1;
		break;
	case 0xc:		// lcr
		data = io.uart.lcr;
		break;
	case 0x10:		// MCR
		data = 0x0;
		break;
	case 0x14:		// LSR
		data = io.uart.lsr;
		//printf("read lsr=%x,pc=%x\n",data,PCREG);
		break;
	case 0x1c:		// SCR
		data = io.uart.lcr;
		break;
	case 0x24:		// SCR
		data = io.uart.gctl;
		break;

	default:
		IO_ERR;
		DBG_PRINT ("uart_read(%s=0x%08x)\n", "uart_reg", addr);

		break;
	}

	return (data);
}


void
uart_write_word (bu32 addr, bu16 data)
{
	bu32 offset = addr - UART_IO_START_ADDR;
	
	   //if(offset != 0 && offset != 0xc)
	   //printf("************offset=%x,value = %x\n",offset,data);
	
	switch (offset) {
	case 0x0:		// THR
		{
			unsigned char c = data & 0xff;
			/*There is no TSR ,so we set TEMT and THRE together */
			io.uart.lsr |= 0x60;
			io.sic.sic_isr &= ~0x8000;
			io.uart.iir = 0x1;

			/* 2007-01-18 modified by Anthony Lee : for new uart device frame */
			skyeye_uart_write(-1, &c, 1, NULL);
		}
		break;
	case 0x4:		//FCR
		/*just walkaround code to open uart */
		if (io.uart.lcr & 0x80) {
			io.uart.dlh = data;
			/*
			   if(data&0x8){
			   printf("KSDBG:UART OPEN\n");
			   UART_OPEN = 1;
			   } */
		}
		else {
			io.uart.ier = data;
			/*generate RX interrupt */
			if (data & 0x1) {
			}
			/*generate TX interrupt */
			if (data & 0x2) {
			}
			if (data & 0x8) {
				UART_OPEN = 1;
			}
		}

		break;
	case 0xc:		// SCR
		io.uart.lcr = data;
		break;
	case 0x24:
		io.uart.gctl = data;
		break;
	default:
		IO_ERR;
		//printf("%c", data); fflush(stdout);
		DBG_PRINT ("uart_write(%s=0x%08x)\n", "uart_reg", addr);
		break;
	}
}
bu32
uart_read_long (bu32 addr)
{
	bu16 ret;
	IO_ERR;
	return ret;
}

void
uart_write_long (bu32 addr, bu32 value)
{
	uart_write_word(addr, (value & 0xffff));
	//IO_ERR;
	return;
}

bu8
uart_read_byte (bu32 addr)
{
	bu8 ret;
	IO_ERR;
	return ret;
}
static void
uart_write_byte (bu32 addr, bu8 value)
{
	IO_ERR;
	return;
}
static bu16
ebiu_read_word (bu32 addr)
{
	int offset = addr - EBIU_IO_START_ADDR;
	switch (offset) {
	case 0:
		return io.ebiu.amgctl;
	case 4:
		return io.ebiu.ambctl0;
	case 8:
		return io.ebiu.ambctl1;
	case 0x10:
		return io.ebiu.sdgctl;
	case 0x1c:
		return io.ebiu.sdstat;
	default:
		IO_ERR;
	}
	return;

}
static bu32
ebiu_read_long (bu32 addr)
{
	int offset = addr - EBIU_IO_START_ADDR;
	switch (offset) {
	case 0:
		return io.ebiu.amgctl;
	case 4:
		return io.ebiu.ambctl0;
	case 8:
		return io.ebiu.ambctl1;
	case 0x10:
		return io.ebiu.sdgctl;
	default:
		IO_ERR;
	}
	return;

}
static void
ebiu_write_long (bu32 addr, bu32 v)
{
	int offset = addr - EBIU_IO_START_ADDR;
	switch (offset) {
	case 0:
		io.ebiu.amgctl = v;
		break;
	case 4:
		io.ebiu.ambctl0 = v;
		break;
	case 8:
		io.ebiu.ambctl1 = v;
		break;
	case 0x10:
		io.ebiu.sdgctl = v;
		break;
	default:
		IO_ERR;
	}
	return;
}
static void
ebiu_write_word (bu32 addr, bu16 v)
{
	int offset = addr - EBIU_IO_START_ADDR;
	switch (offset) {
	case 0:
		io.ebiu.amgctl = v;
		break;
	case 4:
		io.ebiu.ambctl0 = v;
		break;
	case 8:
		io.ebiu.ambctl1 = v;
		break;
	case 0x18:
		io.ebiu.sdrrc = v;
		break;
	default:
		IO_ERR;
	}
	return;
}



static bu8
dma_read_byte (bu32 addr)
{
	bu8 ret = 0;
	IO_ERR;
	return ret;
}
static void
dma_write_byte (bu32 addr, bu8 value)
{
	IO_ERR;
	/*
	   int channel = addr&0x3c0;
	   int offset = (addr&0x3f)>>2;
	   io.dma.bf533_dma_channel[channel][offset] = value;
	 */
	return;
}


static bu16
dma_read_word (bu32 addr)
{
	bu16 ret;
	int channel = (addr & 0x3c0) >> 6;
	int offset = (addr & 0x3f) >> 2;
	ret = io.dma.bf533_dma_channel[channel][offset];
	return ret;
}
static void
dma_write_word (bu32 addr, bu16 value)
{
	int i;
	int channel = (addr & 0x3c0) >> 6;
	int offset = (addr & 0x3f) >> 2;
	DBG_PRINT("\nIn %s,channel=0x%x,offset = %x,value=%x\n",__FUNCTION__, channel,offset,value);
	switch (offset) {
	case 0x2:
		/*CONFIG*/ 
		io.dma.bf533_dma_channel[channel][offset] = value;
		if (!(value & 0x1))
                        break;
		if (channel == BF533_MDMA_D0) {

			unsigned int src =
				io.dma.bf533_dma_channel[BF533_MDMA_S0][START_ADDR];
			unsigned int dst =
				io.dma.bf533_dma_channel[BF533_MDMA_D0][START_ADDR];
			short x_modify =
                                (short)io.dma.bf533_dma_channel[BF533_MDMA_D0][X_MODIFY];
			unsigned int size =
				io.dma.bf533_dma_channel[BF533_MDMA_D0][X_COUNT] * \
				abs(x_modify);

			/* if two-demision is used */
			if(io.dma.bf533_dma_channel[BF533_MDMA_D0][DMA_CONFIG] & 0x10){
				size = size * io.dma.bf533_dma_channel[BF533_MDMA_D0][Y_COUNT] * \
					io.dma.bf533_dma_channel[BF533_MDMA_D0][Y_MODIFY];
			}
			/* if 16 width is used */
			if((((io.dma.bf533_dma_channel[BF533_MDMA_D0][DMA_CONFIG] & 0xc) >> 2)) == 0x1){
				size = size / 2;
			}
			i = size;
			//mem_cpy(start_addr,end_addr,size);

			/*work around code for dma copy to isram */
			/*
 			if (dst >= 0xffa00000) {
				return;
			}*/
				/***************************************/
			DBG_PRINT (
				 "DMA copy begin from 0x%x to 0x%x,size=0x%x\n",
				 src, dst, size);
			for (; i >= 0; i--) {	
				if(x_modify > 0)
					put_byte (saved_state.memory, dst++,
					  get_byte (saved_state.memory,
						    src++));
				else
					 put_byte (saved_state.memory, dst--,
                                          get_byte (saved_state.memory,
                                                    src--));
			}

		}
		break;

	default:
		io.dma.bf533_dma_channel[channel][offset] = value;
		break;
	}
	return;
}
static bu32
dma_read_long (bu32 addr)
{
	bu32 ret;
	int channel = (addr & 0x3c0) >> 6;
	int offset = (addr & 0x3f) >> 2;
	ret = io.dma.bf533_dma_channel[channel][offset];
	return ret;
}
static void
dma_write_long (bu32 addr, bu32 value)
{
	int channel = (addr & 0x3c0) >> 6;
	int offset = (addr & 0x3f) >> 2;
	DBG_PRINT("\nIn %s channel=0x%x,offset = %x,value=%x\n",__FUNCTION__,channel,offset,value); 
	io.dma.bf533_dma_channel[channel][offset] = value;
	return;
}
static void
core_int_write_long (bu32 addr, bu32 v)
{
	int offset = addr - CORE_INT_IO_START_ADDR;
	//printf("%x,%x\n",addr,v);
	switch (offset) {
	case 0x104:
		io.core_int.imask = (v | 0x1f) & 0xffff;
		break;
	case 0x108: