bfin-dis.c

SkyEye是一个可以运行嵌入式操作系统的硬件仿真工具

		PCREG += 2;
		return;
	}
}

static void
decode_CC2dreg_0 (bu16 iw0)
{
/* CC2dreg
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |.op....|.reg.......|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
*/
	int reg = ((iw0 >> 0) & 0x7);
	int op = ((iw0 >> 3) & 0x3);

	if (op == 0) {
		notethat ("dregs = CC");
		DREG (reg) = CCREG;
	}
	else if (op == 1) {
		notethat ("CC = dregs");
		CCREG = DREG (reg) != 0;
	}
	else if (op == 3) {
		notethat ("CC =! CC");
		CCREG = !CCREG;
	}
	else
		unhandled_instruction ();
	PCREG += 2;
}

static void
decode_CC2stat_0 (bu16 iw0)
{
/* CC2stat
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.D.|.op....|.cbit..............|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
*/
	int cbit = ((iw0 >> 0) & 0x1f);
	int D = ((iw0 >> 7) & 0x1);
	int op = ((iw0 >> 5) & 0x3);
	int *pval;

	switch (cbit) {
	case 0:
		pval = &saved_state.az;
		break;
	case 1:
		pval = &saved_state.an;
		break;
	case 6:
		pval = &saved_state.aq;
		break;
	case 12:
		pval = &saved_state.ac0;
		break;
	case 13:
		pval = &saved_state.ac1;
		break;
	case 16:
		pval = &saved_state.av0;
		break;
	case 17:
		pval = &saved_state.av0s;
		break;
	case 18:
		pval = &saved_state.av1;
		break;
	case 19:
		pval = &saved_state.av1s;
		break;
	case 24:
		pval = &saved_state.v;
		break;
	case 25:
		pval = &saved_state.vs;
		break;
	default:
		unhandled_instruction ();
	}

	if (D == 0)
		switch (op) {
		case 0:
			CCREG = *pval;
			break;
		case 1:
			CCREG |= *pval;
			break;
		case 2:
			CCREG &= *pval;
			break;
		case 3:
			CCREG ^= *pval;
			break;
		}
	else
		switch (op) {
		case 0:
			*pval = CCREG;
			break;
		case 1:
			*pval |= CCREG;
			break;
		case 2:
			*pval &= CCREG;
			break;
		case 3:
			*pval ^= CCREG;
			break;
		}
	PCREG += 2;
}

static void
decode_BRCC_0 (bu16 iw0, bu32 pc)
{
/* BRCC
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
| 0 | 0 | 0 | 1 |.T.|.B.|.offset................................|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
*/
	int B = ((iw0 >> 10) & 0x1);
	int T = ((iw0 >> 11) & 0x1);
	int offset = ((iw0 >> 0) & 0x3ff);

	/* B is just the branch predictor hint - we can ignore it.  */

	notethat ("IF CC JUMP pcrel10");
	if (CCREG == T) {
		PCREG += pcrel10 (offset);
		did_jump = 1;
	}
	else
		PCREG += 2;
	return;
}

static void
decode_UJUMP_0 (bu16 iw0, bu32 pc)
{
/* UJUMP
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
| 0 | 0 | 1 | 0 |.offset........................................|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
*/
	int offset = ((iw0 >> 0) & 0xfff);

	notethat ("JUMP.S pcrel12");
	PCREG += pcrel12 (offset);
	did_jump = 1;
}

static void
decode_REGMV_0 (bu16 iw0)
{
/* REGMV
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
| 0 | 0 | 1 | 1 |.gd........|.gs........|.dst.......|.src.......|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
*/
	int src = ((iw0 >> 0) & 0x7);
	int gs = ((iw0 >> 6) & 0x7);
	int dst = ((iw0 >> 3) & 0x7);
	int gd = ((iw0 >> 9) & 0x7);
	int *srcreg = get_allreg (gs, src);
	int *dstreg = get_allreg (gd, dst);

	if (srcreg == 0 || dstreg == 0) {
		printf ("srcreg=%x,dstreg=%x\n", srcreg, dstreg);
		unhandled_instruction ();
	}

	*dstreg = *srcreg;
	PCREG += 2;
	return;
}

static void
decode_ALU2op_0 (bu16 iw0)
{
/* ALU2op
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
| 0 | 1 | 0 | 0 | 0 | 0 |.opc...........|.src.......|.dst.......|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
*/
	int src = ((iw0 >> 3) & 0x7);
	int opc = ((iw0 >> 6) & 0xf);
	int dst = ((iw0 >> 0) & 0x7);

	if (opc == 0) {
		notethat ("dregs >>>= dregs");
		DREG (dst) = ashiftrt (DREG (dst), DREG (src));
	}
	else if (opc == 1) {
		notethat ("dregs >>= dregs");
		DREG (dst) = lshiftrt (DREG (dst), DREG (src));
	}
	else if (opc == 2) {
		notethat ("dregs <<= dregs");
		DREG (dst) = lshift (DREG (dst), DREG (src));
	}
	else if (opc == 3) {
		notethat ("dregs *= dregs");
		DREG (dst) *= DREG (src);
	}
	else if (opc == 4) {
		notethat ("dregs = (dregs + dregs) << 1");
		DREG (dst) = add_and_shift (DREG (dst), DREG (src), 1);
	}
	else if (opc == 5) {
		notethat ("dregs = (dregs + dregs) << 2");
		DREG (dst) = add_and_shift (DREG (dst), DREG (src), 2);
	}
	else if (opc == 8) {
		notethat ("DIVQ (dregs , dregs)");
		OUTS (outf, "DIVQ");
		OUTS (outf, "(");
		OUTS (outf, dregs (dst));
		OUTS (outf, ",");
		OUTS (outf, dregs (src));
		OUTS (outf, ")");
		/*thanks to jie , I understand the DIVQ instn */
		DREG (src) <<= 16;
		if (AQFLAG)
			DREG (dst) = DREG (dst) + DREG (src);
		else
			DREG (dst) = DREG (dst) - DREG (src);
		AQFLAG = ((DREG (dst) & 0x80000000) >> 31) ^
			((DREG (src) & 0x80000000) >> 31);
		DREG (dst) <<= 1;
		if (AQFLAG == 0)
			DREG (dst) += 1;
		DREG (src) >>= 16;
		PCREG += 2;
		return;
	}
	else if (opc == 9) {
		notethat ("DIVS (dregs , dregs)");
		OUTS (outf, "DIVS");
		OUTS (outf, "(");
		OUTS (outf, dregs (dst));
		OUTS (outf, ",");
		OUTS (outf, dregs (src));
		OUTS (outf, ")");
		/*thanks to jie , I understand the DIVQ instn */
		AQFLAG = ((DREG (dst) & 0x80000000) >> 31) ^
			((DREG (src) & 0x80000000) >> 31);
		/*DREG(src) <<= 16;
		   if(AQFLAG)
		   DREG(dst) = DREG(dst) + DREG(src);
		   else
		   DREG(dst) = DREG(dst) - DREG(src);
		   DREG(src) >>= 16;
		 */
		DREG (dst) <<= 1;
		if (AQFLAG == 0)
			DREG (dst) += 1;
		PCREG += 2;
		return;

	}
	else if (opc == 10) {
		notethat ("dregs = dregs_lo (X)");
		DREG (dst) = (bs32) (bs16) DREG (src);
		setflags_logical (DREG (dst));
	}
	else if (opc == 11) {
		notethat ("dregs = dregs_lo (Z)");
		DREG (dst) = (bu32) (bu16) DREG (src);
		setflags_logical (DREG (dst));
	}
	else if (opc == 12) {
		notethat ("dregs = dregs_byte (X)");
		DREG (dst) = (bs32) (bs8) DREG (src);
		setflags_logical (DREG (dst));
	}
	else if (opc == 13) {
		notethat ("dregs = dregs_byte (Z)");
		DREG (dst) = (bu32) (bu8) DREG (src);
		setflags_logical (DREG (dst));
	}
	else if (opc == 14) {
		bu32 val = DREG (src);
		notethat ("dregs = - dregs");
		DREG (dst) = -val;
		setflags_nz (DREG (dst));
		if (val == 0x80000000) {
			saved_state.v = saved_state.vs = 1;
		}
		/* @@@ Documentation isn't entirely clear about av0 and av1.  */
	}
	else if (opc == 15) {
		notethat ("dregs = ~ dregs");
		DREG (dst) = ~DREG (src);
		setflags_logical (DREG (dst));
	}
	else
		unhandled_instruction ();
	PCREG += 2;
	return;
}

static void
decode_PTR2op_0 (bu16 iw0)
{
	/* PTR2op
	   +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
	   | 0 | 1 | 0 | 0 | 0 | 1 | 0 |.opc.......|.src.......|.dst.......|
	   +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
	 */
	int src = ((iw0 >> 3) & 0x7);
	int opc = ((iw0 >> 6) & 0x7);
	int dst = ((iw0 >> 0) & 0x7);

	if (opc == 0)
		PREG (dst) -= PREG (src);
	else if (opc == 1)
		PREG (dst) = PREG (src) << 2;
	else if (opc == 3)
		PREG (dst) = PREG (src) >> 2;
	else if (opc == 4)
		PREG (dst) = PREG (src) >> 1;
	else if (opc == 5) {
		notethat ("pregs += pregs ( BREV )");
		unhandled_instruction ();
		OUTS (outf, pregs (dst));
		OUTS (outf, "+=");
		OUTS (outf, pregs (src));
		OUTS (outf, "(");
		OUTS (outf, "BREV");
		OUTS (outf, ")");
	}
	else if (opc == 6)
		PREG (dst) = (PREG (dst) + PREG (src)) << 1;
	else if (opc == 7)
		PREG (dst) = (PREG (dst) + PREG (src)) << 2;
	else
		unhandled_instruction ();

	PCREG += 2;
	return;
}

static void
decode_LOGI2op_0 (bu16 iw0)
{
/* LOGI2op
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
| 0 | 1 | 0 | 0 | 1 |.opc.......|.src...............|.dst.......|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
*/
	int src = ((iw0 >> 3) & 0x1f);
	int opc = ((iw0 >> 8) & 0x7);
	int dst = ((iw0 >> 0) & 0x7);

	if (opc == 0) {
		notethat ("CC = ! BITTST ( dregs , uimm5 )");
		CCREG = (~DREG (dst) >> uimm5 (src)) & 1;
	}
	else if (opc == 1) {
		notethat ("CC = BITTST ( dregs , uimm5 )");
		CCREG = (DREG (dst) >> uimm5 (src)) & 1;
	}
	else if (opc == 2) {
		notethat ("BITSET ( dregs , uimm5 )");
		DREG (dst) |= 1 << uimm5 (src);
		setflags_logical (DREG (dst));
	}
	else if (opc == 3) {
		notethat ("BITTGL ( dregs , uimm5 )");
		DREG (dst) ^= 1 << uimm5 (src);
		setflags_logical (DREG (dst));
	}
	else if (opc == 4) {
		notethat ("BITCLR ( dregs , uimm5 )");
		DREG (dst) &= ~(1 << uimm5 (src));
		setflags_logical (DREG (dst));
	}
	else if (opc == 5) {
		notethat ("dregs >>>= uimm5");
		DREG (dst) = ashiftrt (DREG (dst), uimm5 (src));
	}
	else if (opc == 6) {
		notethat ("dregs >>= uimm5");
		DREG (dst) = lshiftrt (DREG (dst), uimm5 (src));
	}
	else if (opc == 7) {
		notethat ("dregs <<= uimm5");
		DREG (dst) = lshift (DREG (dst), uimm5 (src));
	}
	PCREG += 2;
	return;
}

static void
decode_COMP3op_0 (bu16 iw0)
{
	/* COMP3op
	   +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
	   | 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......|
	   +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
	 */
	int src0 = ((iw0 >> 0) & 0x7);
	int src1 = ((iw0 >> 3) & 0x7);
	int opc = ((iw0 >> 9) & 0x7);
	int dst = ((iw0 >> 6) & 0x7);


	if (opc == 0) {
		notethat ("dregs = dregs + dregs");
		DREG (dst) = add32 (DREG (src0), DREG (src1), 1);
	}
	else if (opc == 1) {
		notethat ("dregs = dregs - dregs");
		DREG (dst) = sub32 (DREG (src0), DREG (src1), 1);
	}
	else if (opc == 2) {
		notethat ("dregs = dregs & dregs");
		DREG (dst) = DREG (src0) & DREG (src1);
		setflags_logical (DREG (dst));
	}
	else if (opc == 3) {
		notethat ("dregs = dregs | dregs");
		DREG (dst) = DREG (src0) | DREG (src1);
		setflags_logical (DREG (dst));
	}
	else if (opc == 4) {
		notethat ("dregs = dregs ^ dregs");
		DREG (dst) = DREG (src0) ^ DREG (src1);
		setflags_logical (DREG (dst));
	}
	else if (opc == 5)
		/* If src0 == src1 this is disassembled as a shift by 1, but this
		   distinction doesn't matter for our purposes.  */
		PREG (dst) = PREG (src0) + PREG (src1);
	else if (opc == 6)
		PREG (dst) = PREG (src0) + (PREG (src1) << 1);
	else if (opc == 7)
		PREG (dst) = PREG (src0) + (PREG (src1) << 2);

	PCREG += 2;
	return;
}

static void
decode_COMPI2opD_0 (bu16 iw0)
{
/* COMPI2opD
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
| 0 | 1 | 1 | 0 | 0 |.op|.isrc......................|.dst.......|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
*/
	int isrc = ((iw0 >> 3) & 0x7f);
	int dst = ((iw0 >> 0) & 0x7);
	int op = ((iw0 >> 10) & 0x1);

	if (op == 0)
		DREG (dst) = imm7 (isrc);
	else if (op == 1)
		DREG (dst) = add32 (DREG (dst), imm7 (isrc), 1);
	PCREG += 2;
	return;
}

static void
decode_COMPI2opP_0 (bu16 iw0)
{
/* COMPI2opP
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
| 0 | 1 | 1 | 0 | 1 |.op|.src.......................|.dst.......|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
*/
	int src = ((iw0 >> 3) & 0x7f);
	int dst = ((iw0 >> 0) & 0x7);
	int op = ((iw0 >> 10) & 0x1);

	if (op == 0)
		PREG (dst) = imm7 (src);
	else if (op == 1)
		PREG (dst) += imm7 (src);
	PCREG += 2;
	return;
}

static void
decode_LDSTpmod_0 (bu16 iw0)
{
/* LDSTpmod
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
| 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......|
+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
*/
	int aop = ((iw0 >> 9) & 0x3);
	int idx = ((iw0 >> 3) & 0x7);
	int ptr = ((iw0 >> 0) & 0x7);
	int reg = ((iw0 >> 6) & 0x7);
	int W = ((iw0 >> 11) & 0x1);
	bu32 addr, val;

	if (aop == 1 && W == 0 && idx == ptr) {
		notethat ("dregs_lo = W [ pregs ]");
		addr = PREG (ptr);
		val = get_word (saved_state.memory, addr);
		STORE (DREG (reg), (DREG (reg) & 0xFFFF0000) | val);
		PCREG += 2;
		return;
	}
	else if (aop == 2 && W == 0 && idx == ptr) {
		notethat ("dregs_hi = W [ pregs ]");
		addr = PREG (ptr);
		val = get_word (saved_state.memory, addr);
		STORE (DREG (reg), (DREG (reg) & 0xFFFF) | (val << 16));
		PCREG += 2;
		return;
	}
	else if (aop == 1 && W == 1 && idx == ptr) {
		notethat ("W [ pregs ] = dregs_lo");
		addr = PREG (ptr);
		put_word (saved_state.memory, addr, DREG (reg));
		PCREG += 2;
		return;
	}
	else if (aop == 2 && W == 1 && idx == ptr) {
		notethat ("W [ pregs ] = dregs_hi");
		addr = PREG (ptr);
		put_word (saved_state.memory, addr, DREG (reg) >> 16);
		PCREG += 2;
		return;
	}
	else if (aop == 0 && W == 0) {
		notethat ("dregs = [ pregs ++ pregs ]");
		addr = PREG (ptr);
		val = get_long (saved_state.memory, addr);
		STORE (DREG (reg), val);
		STORE (PREG (ptr), addr + PREG (idx));
		PCREG += 2;
		return;
	}
	else if (aop == 1 && W == 0) {
		notethat ("dregs_lo = W [ pregs ++ pregs ]");
		addr = PREG (ptr);
		val = get_word (saved_state.memory, addr);
		STORE (DREG (reg), (DREG (reg) & 0xFFFF0000) | val);