📄 bfin-dis.c
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case 1: *accum = acc + res; break; case 2: *accum = acc - res; break; } /* Saturate. */ switch (mmod) { case 0: case M_T: case M_IS: case M_ISS2: case M_S2RND: if ((bs64) * accum < -0x8000000000ll) *accum = -0x8000000000ull; else if ((bs64) * accum >= 0x7fffffffffll) *accum = 0x7fffffffffull; break; case M_TFU: case M_FU: case M_IU: if (*accum > 0xFFFFFFFFFFull) *accum = 0xFFFFFFFFFFull; break; default: abort (); } acc = *accum; } return extract_mult (acc, mmod, fullword);}static voiddecode_ProgCtrl_0 (bu16 iw0){/* ProgCtrl+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.prgfunc.......|.poprnd........|+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+*/ int poprnd = ((iw0 >> 0) & 0xf); int prgfunc = ((iw0 >> 4) & 0xf); //PRINTF("\npoprud=%x,prgfunc=%x\n",poprnd,prgfunc); if (prgfunc == 0 && poprnd == 0) { //notethat ("NOP"); //PRINTF("NULL meory,pc=0x%x\n",PCREG);// fprintf(PF,"##############################NOP,pc=%x\n",PCREG); PCREG += 2; return; } else if (prgfunc == 1 && poprnd == 0) { //notethat ("RTS"); //PRINTF("DEBUG:pc = 0x%x\n",saved_state.rets); PCREG = RETSREG; return; } else if (prgfunc == 1 && poprnd == 1) { //PRINTF("DEBUG33\n"); //notethat ("RTI"); //OUTS (outf, "RTI"); /*0 is meaningless */ PCREG = RETIREG; /*clear global int bit in ipend */ saved_state.enable_int (); /*clear the responding pending bit */ saved_state.clear_int (0); //did_jump = 1; return; } else if (prgfunc == 1 && poprnd == 2) { notethat ("RTX"); OUTS (outf, "RTX"); //unhandled_instruction (); //fprintf(PF,"RTX\n"); /*clear global int bit in ipend */ saved_state.enable_int (); /*clear the responding pending bit */ saved_state.clear_int (0); PCREG = RETXREG; return; } else if (prgfunc == 1 && poprnd == 3) { notethat ("RTN"); OUTS (outf, "RTN"); unhandled_instruction (); PCREG = RETNREG; return; } else if (prgfunc == 1 && poprnd == 4) { notethat ("RTE"); OUTS (outf, "RTE"); unhandled_instruction (); PCREG = RETEREG; return; } else if (prgfunc == 2 && poprnd == 0) { notethat ("IDLE"); OUTS (outf, "IDLE"); //unhandled_instruction (); PCREG += 2; return; } else if (prgfunc == 2 && poprnd == 3) {// PRINTF("DEBUG22\n"); //notethat ("CSYNC"); //OUTS (outf, "CSYNC"); PCREG += 2; return; } else if (prgfunc == 2 && poprnd == 4) { // PRINTF("DEBUG11\n"); //notethat ("SSYNC"); //PRINTF("SSYNC"); //OUTS (outf, "SSYNC"); PCREG += 2; return; } else if (prgfunc == 2 && poprnd == 5) { notethat ("EMUEXCPT"); OUTS (outf, "EMUEXCPT"); unhandled_instruction (); PCREG += 2; return; } else if (prgfunc == 3) { // notethat ("CLI dregs"); // OUTS (outf, "CLI "); //OUTS (outf, dregs (poprnd)); saved_state.cli (&DREG (poprnd)); PCREG += 2; return; } else if (prgfunc == 4) { //notethat ("STI dregs"); // OUTS (outf, "STI"); // OUTS (outf, dregs (poprnd)); saved_state.sti (&DREG (poprnd)); PCREG += 2; return; } else if (prgfunc == 5) { notethat ("JUMP ( pregs )"); PCREG = PREG (poprnd); did_jump = 1; return; } else if (prgfunc == 6) { notethat ("CALL ( pregs )"); saved_state.rets = PCREG + 2; PCREG = PREG (poprnd); did_jump = 1; return; } else if (prgfunc == 7) { notethat ("CALL ( PC + pregs )"); saved_state.rets = PCREG + 2; PCREG = PCREG + PREG (poprnd); did_jump = 1; return; } else if (prgfunc == 8) { notethat ("JUMP ( PC + pregs )"); PCREG = PCREG + PREG (poprnd); did_jump = 1; return; } else if (prgfunc == 9) { extern int raise_flag; notethat ("RAISE uimm4"); //bfin_trap (); saved_state.set_int (poprnd); raise_flag = 1; PCREG += 2; return; } else if (prgfunc == 10) { notethat ("EXCPT uimm4"); if (uimm4 (poprnd) == 1) { //raise_exception(SIGTRAP); // single step exception dont increment PCREG ... PCREG += 2; return; } else { //fprintf(stderr, "unhandled exception1\n"); OUTS (outf, "EXCPT "); OUTS (outf, uimm4 (poprnd)); //fprintf(PF,"System call :pc=0x%x,oldpc=0x%x,olderpc=0x%x,EXCPT %x\n",PCREG,OLDPCREG,OLDERPCREG,uimm4 (poprnd)); saved_state.set_int (3); SEQSTATREG = SEQSTATREG & 0xffffffc0 + poprnd & 0x3f; //unhandled_instruction (); PCREG += 2; return; } } else if (prgfunc == 11) { notethat ("TESTSET ( pregs )"); OUTS (outf, "TESTSET "); OUTS (outf, "("); OUTS (outf, pregs (poprnd)); OUTS (outf, ")"); unhandled_instruction (); PCREG += 2; return; } else unhandled_instruction ();}#define NOT_IMP {fprintf(stderr,"pc=0x%x,p0=0x%x,p1=0x%x,not implemented cache ops \n",PCREG,PREG(0),PREG(1)); }static voiddecode_CaCTRL_0 (bu16 iw0){/* CaCTRL+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......|+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+*/ int a = ((iw0 >> 5) & 0x1); int reg = ((iw0 >> 0) & 0x7); int op = ((iw0 >> 3) & 0x3); if (a == 0 && op == 0) { notethat ("PREFETCH [ pregs ]"); OUTS (outf, "PREFETCH"); OUTS (outf, "["); OUTS (outf, pregs (reg)); OUTS (outf, "]"); NOT_IMP; PCREG += 2; return; } else if (a == 0 && op == 1) { notethat ("FLUSHINV [ pregs ]"); OUTS (outf, "FLUSHINV"); OUTS (outf, "["); OUTS (outf, pregs (reg)); OUTS (outf, "]"); NOT_IMP; PCREG += 2; return; } else if (a == 0 && op == 2) { notethat ("FLUSH [ pregs ]"); OUTS (outf, "FLUSH"); OUTS (outf, "["); OUTS (outf, pregs (reg)); NOT_IMP; OUTS (outf, "]"); PCREG += 2; return; } else if (a == 0 && op == 3) { notethat ("IFLUSH [ pregs ]"); OUTS (outf, "IFLUSH"); OUTS (outf, "["); OUTS (outf, pregs (reg)); OUTS (outf, "]"); //unhandled_instruction (); NOT_IMP; PCREG += 2; return; } else if (a == 1 && op == 0) { notethat ("PREFETCH [ pregs ++ ]"); OUTS (outf, "PREFETCH"); OUTS (outf, "["); OUTS (outf, pregs (reg)); OUTS (outf, "++"); OUTS (outf, "]"); PREG (reg)++; //NOT_IMP; PCREG += 2; return; } else if (a == 1 && op == 1) { notethat ("FLUSHINV [ pregs ++ ]"); OUTS (outf, "FLUSHINV"); OUTS (outf, "["); OUTS (outf, pregs (reg)); OUTS (outf, "++"); OUTS (outf, "]"); PREG (reg)++; //NOT_IMP; PCREG += 2; return; } else if (a == 1 && op == 2) { notethat ("FLUSH [ pregs ++ ]"); OUTS (outf, "FLUSH"); OUTS (outf, "["); OUTS (outf, pregs (reg)); OUTS (outf, "++"); OUTS (outf, "]"); PREG (reg)++; NOT_IMP; PCREG += 2; return; } else if (a == 1 && op == 3) { notethat ("IFLUSH [ pregs ++ ]"); OUTS (outf, "IFLUSH"); OUTS (outf, "["); OUTS (outf, pregs (reg)); OUTS (outf, "++"); OUTS (outf, "]"); PREG (reg)++; NOT_IMP; PCREG += 2; return; } else unhandled_instruction ();}static voiddecode_PushPopReg_0 (bu16 iw0){/* PushPopReg+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.W.|.grp.......|.reg.......|+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+*/ int grp = ((iw0 >> 3) & 0x7); int reg = ((iw0 >> 0) & 0x7); int W = ((iw0 >> 6) & 0x1); int *whichreg = get_allreg (grp, reg); if (whichreg == 0) { unhandled_instruction (); } if (W == 0) { bu32 word; notethat ("allregs = [ SP ++ ]"); *whichreg = get_long (saved_state.memory, PREG (6)); if (whichreg == &RETIREG) { /*disable the global int bit,until RTI is executed!Or other int maybe overwrite reti */ saved_state.disable_int (); } if (whichreg == &ASTATREG) { /*at the same time,restore CCREG */ CCREG = (ASTATREG & 0x20) >> 5; AZFLAG = ASTATREG & 0x1; AQFLAG = ASTATREG & 0x40 >> 6; //fprintf(PF,"pc=%x,restore cc=%x,SP=0x%x,astat=%x\n\n",PCREG,CCREG,PREG(6),ASTATREG); } PREG (6) += 4; } else { bu32 word; notethat ("[ -- SP ] = allregs"); PREG (6) -= 4; if (whichreg == &RETIREG) { /*enable the global int bit */ saved_state.enable_int (); } if (whichreg == &ASTATREG) { /*at the same time,save CCREG */ ASTATREG = AZFLAG ? (ASTATREG | 0x1) : (ASTATREG & (~0x1)); ASTATREG = CCREG ? (ASTATREG | 0x20) : (ASTATREG & (~0x20)); ASTATREG = AQFLAG ? (ASTATREG | 0x40) : (ASTATREG & (~0x40)); //fprintf(PF,"\npc=%x,save cc=%x,SP=0x%x,astat=%x\n",PCREG,CCREG,PREG(6),ASTATREG); } put_long (saved_state.memory, PREG (6), *whichreg); }/* if(PCREG >= 0x000087f8,PCREG <= 0x88cc) printf("iw0=0x%x,pc=0x%x\n",iw0,PCREG);*/ PCREG += 2; return;}static voiddecode_PushPopMultiple_0 (bu16 iw0){/* PushPopMultiple+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+| 0 | 0 | 0 | 0 | 0 | 1 | 0 |.d.|.p.|.W.|.dr........|.pr........|+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+*/ int p = ((iw0 >> 7) & 0x1); int pr = ((iw0 >> 0) & 0x7); int d = ((iw0 >> 8) & 0x1); int dr = ((iw0 >> 3) & 0x7); int W = ((iw0 >> 6) & 0x1); int i; bu32 sp = PREG (6); if (d == 0 && p == 0) unhandled_instruction (); if (p && imm5 (pr) > 5) unhandled_instruction (); if (W == 1) { if (d) for (i = dr; i < 8; i++) { sp -= 4; put_long (saved_state.memory, sp, DREG (i)); } if (p) for (i = pr; i < 6; i++) { sp -= 4; put_long (saved_state.memory, sp, PREG (i)); } } else { if (p) for (i = 5; i >= pr; i--) { PREG (i) = get_long (saved_state.memory, sp); sp += 4; } if (d) for (i = 7; i >= dr; i--) { DREG (i) = get_long (saved_state.memory, sp); sp += 4; } } PREG (6) = sp; PCREG += 2; return;}static voiddecode_ccMV_0 (bu16 iw0){/* ccMV+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+| 0 | 0 | 0 | 0 | 0 | 1 | 1 |.T.|.d.|.s.|.dst.......|.src.......|+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+*/ int src = ((iw0 >> 0) & 0x7); int dst = ((iw0 >> 3) & 0x7); int s = ((iw0 >> 6) & 0x1); int d = ((iw0 >> 7) & 0x1); int T = ((iw0 >> 8) & 0x1); int cond = T ? CCREG : !CCREG; if (cond) GREG (dst, d) = GREG (src, s); PCREG += 2; return;}static voiddecode_CCflag_0 (bu16 iw0){ /* CCflag +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ | 0 | 0 | 0 | 0 | 1 |.I.|.opc.......|.G.|.y.........|.x.........| +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */ int x = ((iw0 >> 0) & 0x7); int y = ((iw0 >> 3) & 0x7); int I = ((iw0 >> 10) & 0x1); int opc = ((iw0 >> 7) & 0x7); int G = ((iw0 >> 6) & 0x1); if (opc > 4) { if (opc == 5 && I == 0 && G == 0) { notethat ("CC = A0 == A1"); OUTS (outf, "CC"); OUTS (outf, "="); OUTS (outf, "A0"); OUTS (outf, "=="); OUTS (outf, "A1"); unhandled_instruction (); PCREG += 2; return; } else if (opc == 6 && I == 0 && G == 0) { notethat ("CC = A0 < A1"); OUTS (outf, "CC"); OUTS (outf, "="); OUTS (outf, "A0"); OUTS (outf, "<"); OUTS (outf, "A1"); unhandled_instruction (); PCREG += 2; return; } else if (opc == 7 && I == 0 && G == 0) { notethat ("CC = A0 <= A1"); OUTS (outf, "CC"); OUTS (outf, "="); OUTS (outf, "A0"); OUTS (outf, "<="); OUTS (outf, "A1"); unhandled_instruction (); PCREG += 2; return; } } else { int issigned = opc < 3; bu32 srcop = G ? PREG (x) : DREG (x); bu32 dstop = I ? (issigned ? imm3 (y) : uimm3 (y)) : G ? PREG (y) : DREG (y); int flgs = srcop >> 31; int flgo = dstop >> 31; bu32 result = srcop - dstop; int flgn = result >> 31; int overflow = (flgs ^ flgo) & (flgn ^ flgs); saved_state.az = result == 0; saved_state.an = flgn; saved_state.ac0 = srcop < dstop; switch (opc) { case 0: /* == */ CCREG = saved_state.az; break; case 1: /* <, signed */ CCREG = (flgn && !overflow) || (!flgn && overflow); break; case 2: /* <=, signed */ CCREG = (flgn && !overflow) || (!flgn && overflow) || saved_state.az; break; case 3: /* <, unsigned */ CCREG = saved_state.ac0; break; case 4: /* <=, unsigned */ CCREG = saved_state.ac0 | saved_state.az; break; }
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