bfin-dis.c

SkyEye是一个可以运行嵌入式操作系统的硬件仿真工具

#define regs_hi(x,i) REGNAME(decode_regs_hi[((i)<<3)|x])

/* AZ AN AC AV0 AV1 - AQ -                  -  -  -  -   -   -  - -                  -  -  -  -   -   -  - -                  -  -  -  -   -   -  - -  */
static enum machine_registers decode_statbits[] = {
	REG_AZ, REG_AN, REG_AC, REG_AV0, REG_AV1, REG_LASTREG, REG_AQ,
		REG_LASTREG,
	REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
	REG_LASTREG, REG_LASTREG, REG_LASTREG,
	REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
	REG_LASTREG, REG_LASTREG, REG_LASTREG,
	REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
	REG_LASTREG, REG_LASTREG, REG_LASTREG,
};

/*static enum machine_registers decode_statbits[] = {
  REG_AZ,      REG_AN,      REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_AQ,      REG_LASTREG,
  REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_AC0, 	   REG_AC1,     REG_LASTREG, REG_LASTREG,
  REG_AV0,     REG_LASTREG, REG_AV1, 	 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
  REG_V,       REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
  };*/

#define statbits(x) REGNAME(decode_statbits[(x) & 31])

/* sftreset omode excause emucause idle_req hwerrcause */
static enum machine_registers decode_ignore_bits[] = {
	REG_sftreset, REG_omode, REG_excause, REG_emucause, REG_idle_req,
	REG_hwerrcause,
};

#define ignore_bits(x) REGNAME(decode_ignore_bits[(x) & 7])

/* CC  */
static enum machine_registers decode_ccstat[] = {
	REG_CC,
};

#define ccstat(x) REGNAME(decode_ccstat[(x) & 0])

/* LC0 LC1  */
static enum machine_registers decode_counters[] = {
	REG_LC0, REG_LC1,
};

#define counters(x) REGNAME(decode_counters[(x) & 1])

/* A0x A0w A1x A1w GP - ASTAT RETS  */
static enum machine_registers decode_dregs2_sysregs1[] = {
	REG_A0x, REG_A0w, REG_A1x, REG_A1w, REG_GP, REG_LASTREG, REG_ASTAT,
	REG_RETS,
};

#define dregs2_sysregs1(x) REGNAME(decode_dregs2_sysregs1[(x) & 7])

/* - - - - - - - - */
static enum machine_registers decode_open[] = {
	REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
	REG_LASTREG, REG_LASTREG, REG_LASTREG,
};

#define open(x) REGNAME(decode_open[(x) & 7])

/* LC0 LT0 LB0 LC1 LT1 LB1 CYCLES CYCLES2 */
static enum machine_registers decode_sysregs2[] = {
	REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES,
	REG_CYCLES2,
};

#define sysregs2(x) REGNAME(decode_sysregs2[(x) & 7])

/* USP SEQSTAT SYSCFG RETI RETX RETN RETE - */
static enum machine_registers decode_sysregs3[] = {
	REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN,
		REG_RETE,
	REG_LASTREG,
};

#define sysregs3(x) REGNAME(decode_sysregs3[(x) &7])

/* [dregs pregs (iregs mregs) (bregs lregs) 	         dregs2_sysregs1 open sysregs2 sysregs3] */
static enum machine_registers decode_allregs[] = {
	REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
	REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
	REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
	REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
	REG_A0x, REG_A0w, REG_A1x, REG_A1w, REG_GP, REG_LASTREG, REG_ASTAT,
	REG_RETS,
	REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
	REG_LASTREG, REG_LASTREG, REG_LASTREG,
	REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES,
	REG_CYCLES2,
	REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN,
		REG_RETE,
	REG_LASTREG,
};

#define allregs(x,i) REGNAME(decode_allregs[((i)<<3)|x])
#define uimm16s4(x) fmtconst(c_uimm16s4, x, 0)
#define pcrel4(x) fmtconst(c_pcrel4, x, pc)
#define pcrel8(x) fmtconst(c_pcrel8, x, pc)
#define pcrel8s4(x) fmtconst(c_pcrel8s4, x, pc)
#define pcrel10(x) fmtconst(c_pcrel10, x, pc)
#define pcrel12(x) fmtconst(c_pcrel12, x, pc)
#define negimm5s4(x) fmtconst(c_negimm5s4, x, 0)
#define rimm16(x) fmtconst(c_rimm16, x, 0)
#define huimm16(x) fmtconst(c_huimm16, x, 0)
#define imm16(x) fmtconst(c_imm16, x, 0)
#define uimm2(x) fmtconst(c_uimm2, x, 0)
#define uimm3(x) fmtconst(c_uimm3, x, 0)
#define luimm16(x) fmtconst(c_luimm16, x, 0)
#define uimm4(x) fmtconst(c_uimm4, x, 0)
#define uimm5(x) fmtconst(c_uimm5, x, 0)
#define imm16s2(x) fmtconst(c_imm16s2, x, 0)
#define uimm8(x) fmtconst(c_uimm8, x, 0)
#define imm16s4(x) fmtconst(c_imm16s4, x, 0)
#define uimm4s2(x) fmtconst(c_uimm4s2, x, 0)
#define uimm4s4(x) fmtconst(c_uimm4s4, x, 0)
#define lppcrel10(x) fmtconst(c_lppcrel10, x, pc)
#define imm3(x) fmtconst(c_imm3, x, 0)
#define imm4(x) fmtconst(c_imm4, x, 0)
#define uimm8s4(x) fmtconst(c_uimm8s4, x, 0)
#define imm5(x) fmtconst(c_imm5, x, 0)
#define imm6(x) fmtconst(c_imm6, x, 0)
#define imm7(x) fmtconst(c_imm7, x, 0)
#define imm8(x) fmtconst(c_imm8, x, 0)
#define pcrel24(x) fmtconst(c_pcrel24, x, pc)
#define uimm16(x) fmtconst(c_uimm16, x, 0)

/* (arch.pm)arch_disassembler_functions */
//#define notethat(x) printf("%s",x)
#define notethat(x)


//#define OUTS(p,txt) unhandled_instruction ()
#define OUTS(p,txt)

static int *
get_allreg (int grp, int reg)
{
	int fullreg = (grp << 3) | reg;
	/* REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
	   REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
	   REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
	   REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
	   REG_A0x, REG_A0w, REG_A1x, REG_A1w, REG_GP, REG_LASTREG, REG_ASTAT,
	   REG_RETS,
	   REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
	   REG_LASTREG, REG_LASTREG, REG_LASTREG,
	   REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES,
	   REG_CYCLES2,
	   REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE,
	   REG_LASTREG */
	switch (fullreg >> 2) {
	case 0:
	case 1:
		return &DREG (reg);
		break;
	case 2:
	case 3:
		return &PREG (reg);
		break;
	case 4:
		return &IREG (reg & 3);
		break;
	case 5:
		return &MREG (reg & 3);
		break;
	case 6:
		return &BREG (reg & 3);
		break;
	case 7:
		return &LREG (reg & 3);
		break;
	default:
		//printf("fullreg=%x,group=%d\n",fullreg,fullreg >> 2);
		switch (fullreg) {
		case 0x20:
			return &A0XREG;
		case 0x21:
			return &A0WREG;
		case 0x22:
			return &A1XREG;
		case 0x23:
			return &A1WREG;
		case 0x26:
			return &ASTATREG;
		case 0x27:
			return &saved_state.rets;
		case 0x30:
			return &saved_state.lc[0];
		case 0x31:
			return &saved_state.lt[0];
		case 0x32:
			return &saved_state.lb[0];
		case 0x33:
			return &saved_state.lc[1];
		case 0x34:
			return &saved_state.lt[1];
		case 0x35:
			return &saved_state.lb[1];
		case 0x38:
			return &saved_state.usp;
		case 0x39:
			return &saved_state.syscfg;
		case 0x3a:
			return &SEQSTATREG;
		case 0x3b:
			return &RETIREG;
		case 0x3c:
			return &RETXREG;
		case 0x3d:
			return &RETNREG;
		case 0x3e:
			return &RETEREG;

			//printf("reg_syscfg\n");
		}
		printf ("invalid register,fullreg=%x\n", fullreg);
		return 0;
	}
}

static void
amod0 (int s0, int x0, bu32 pc)
{
	if (s0 == 0 && x0 == 0) {
		notethat ("(NS)");
		return;
	}
	else if (s0 == 1 && x0 == 0) {
		notethat ("(S)");
		OUTS (outf, "(S)");
		return;
	}
	else if (s0 == 0 && x0 == 1) {
		notethat ("(CO)");
		OUTS (outf, "(CO)");
		return;
	}
	else if (s0 == 1 && x0 == 1) {
		notethat ("(SCO)");
		OUTS (outf, "(SCO)");
		return;
	}
	else
		goto illegal_instruction;
      illegal_instruction:
	return;
}

static void
amod1 (int s0, int x0, bu32 pc)
{
	if (s0 == 0 && x0 == 0) {
		//notethat ("(NS)");
		//OUTS (outf, "(NS)");
		return;
	}
	else if (s0 == 1 && x0 == 0) {
		//notethat ("(S)");
		// OUTS (outf, "(S)");
		return;
	}
	else
		goto illegal_instruction;
      illegal_instruction:
	return;
}

static void
macmod_accm (int mod, bu32 pc)
{
	if (mod == 0) {
		notethat ("");
		return;
	}
	else if (mod == 8) {
		notethat ("(IS)");
		OUTS (outf, "(IS)");
		return;
	}
	else if (mod == 4) {
		notethat ("(FU)");
		OUTS (outf, "(FU)");
		return;
	}
	else if (mod == 3) {
		notethat ("(W32)");
		OUTS (outf, "(W32)");
		return;
	}
	else
		goto illegal_instruction;
      illegal_instruction:
	return;
}

static void
searchmod (int r0, bu32 pc)
{
	if (r0 == 0) {
		notethat ("GT");
		OUTS (outf, "GT");
		return;
	}
	else if (r0 == 1) {
		notethat ("GE");
		OUTS (outf, "GE");
		return;
	}
	else if (r0 == 2) {
		notethat ("LT");
		OUTS (outf, "LT");
		return;
	}
	else if (r0 == 3) {
		notethat ("LE");
		OUTS (outf, "LE");
		return;
	}
	else
		goto illegal_instruction;
      illegal_instruction:
	return;
}


static void
mxd_mod (int mod, bu32 pc)
{


	if (mod == 0) {
		notethat ("");
		return;
	}
	else if (mod == 1) {
		notethat ("(M)");
		OUTS (outf, "(M)");
		return;
	}
	else
		goto illegal_instruction;
      illegal_instruction:
	return;
}

static void
aligndir (int r0, bu32 pc)
{


	if (r0 == 0) {
		notethat ("");
		return;
	}
	else if (r0 == 1) {
		notethat ("(R)");
		OUTS (outf, "(R)");
		return;
	}
	else
		goto illegal_instruction;
      illegal_instruction:
	return;
}

/* Perform a multiplication, sign- or zero-extending the result to 64 bit.  */
static bu64
decode_multfunc (int h0, int h1, int src0, int src1, int mmod, int MM)
{
	bu32 s0 = DREG (src0), s1 = DREG (src1);
	bu32 sgn0, sgn1;
	bu32 val;
	bu64 val1;

	if (h0)
		s0 >>= 16;

	if (h1)
		s1 >>= 16;

	s0 &= 0xffff;
	s1 &= 0xffff;

	sgn0 = -(s0 & 0x8000);
	sgn1 = -(s1 & 0x8000);

	if (MM)
		s0 |= sgn0;
	else
		switch (mmod) {
		case 0:
		case M_S2RND:
		case M_T:
		case M_IS:
		case M_ISS2:
		case M_IH:
			s0 |= sgn0;
			s1 |= sgn1;
			break;
		case M_FU:
		case M_IU:
		case M_TFU:
			break;
		default:
			abort ();
		}

	val = s0 * s1;
	/* Perform shift correction if appropriate for the mode.  */
	if (mmod == 0 || mmod == M_T || mmod == M_S2RND) {
		if (val == 0x40000000)
			val = 0x7fffffff;
		else
			val <<= 1;
	}

	val1 = val;
	if (mmod == 0 || mmod == M_IS || mmod == M_T || mmod == M_S2RND
	    || mmod == M_ISS2 || mmod == M_IH)
		val1 |= -(val1 & 0x80000000);

	return val1;
}

static bu32
saturate_s32 (bu64 val)
{
	if ((bs64) val < -0x80000000ll)
		return 0x80000000;
	if ((bs64) val > 0x7fffffff)
		return 0x7fffffff;
	return val;
}

static bu32
saturate_s16 (bu64 val)
{
	if ((bs64) val < -0x8000ll)
		return 0x8000;
	if ((bs64) val > 0x7fff)
		return 0x7fff;
	return val;
}

static bu32
saturate_u32 (bu64 val)
{
	if (val > 0xffffffff)
		return 0xffffffff;
	return val;
}

static bu32
saturate_u16 (bu64 val)
{
	if (val > 0xffff)
		return 0xffff;
	return val;
}

static bu64
rnd16 (bu64 val)
{
	bu64 sgnbits = val & 0xff00000000000000ull;
	/* @@@ Should honour rounding mode.  Can this overflow?  */
	val += 0x8000;
	val >>= 16;
	return val | sgnbits;

}

static bu64
trunc16 (bu64 val)
{
	bu64 sgnbits = val & 0xff00000000000000ull;
	val >>= 16;
	return val | sgnbits;
}

/* Extract a 16 or 32 bit value from a 64 bit multiplication result.
   These 64 bits must be sign- or zero-extended properly from the source
   we want to extract, either a 32 bit multiply or a 40 bit accumulator.  */

static bu32
extract_mult (bu64 res, int mmod, int fullword)
{
	if (fullword)
		switch (mmod) {
		case 0:
		case M_IS:
			return saturate_s32 (res);
		case M_FU:
			return saturate_u32 (res);
		case M_S2RND:
		case M_ISS2:
			return saturate_s32 (res << 1);
		default:
			abort ();
		}
	else
		switch (mmod) {
		case 0:
		case M_IH:
			return saturate_s16 (rnd16 (res));
		case M_IS:
			return saturate_s16 (res);
		case M_FU:
			return saturate_u16 (rnd16 (res));
		case M_IU:
			return saturate_u16 (res);

		case M_T:
			return saturate_s16 (trunc16 (res));
		case M_TFU:
			return saturate_u16 (trunc16 (res));

		case M_S2RND:
			return saturate_s16 (rnd16 (res << 1));
		case M_ISS2:
			return saturate_s16 (res << 1);
		default:
			abort ();
		}
}

static bu32
decode_macfunc (int which, int op, int h0, int h1, int src0, int src1,
		int mmod, int MM, int fullword)
{
	bu64 *accum = which ? &A1REG : &A0REG;
	bu64 acc = *accum & 0xFFFFFFFFFFull;

	/* Sign extend accumulator if necessary.  */
	if (mmod == 0 || mmod == M_T || mmod == M_IS || mmod == M_ISS2
	    || mmod == M_S2RND)
		acc |= -(acc & 0x80000000);

	if (op != 3) {
		bu64 res = decode_multfunc (h0, h1, src0, src1, mmod, MM);

		/* Perform accumulation.  */
		switch (op) {
		case 0:
			*accum = res;
			break;