📄 clps9312.h
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#define VIC0VECTCNTL03 (VIC0_BASE+0x20C) /* R/W Vector control 03 register */#define VIC0VECTCNTL04 (VIC0_BASE+0x210) /* R/W Vector control 04 register */#define VIC0VECTCNTL05 (VIC0_BASE+0x214) /* R/W Vector control 05 register */#define VIC0VECTCNTL06 (VIC0_BASE+0x218) /* R/W Vector control 06 register */#define VIC0VECTCNTL07 (VIC0_BASE+0x21C) /* R/W Vector control 07 register */#define VIC0VECTCNTL08 (VIC0_BASE+0x220) /* R/W Vector control 08 register */#define VIC0VECTCNTL09 (VIC0_BASE+0x224) /* R/W Vector control 09 register */#define VIC0VECTCNTL10 (VIC0_BASE+0x228) /* R/W Vector control 10 register */#define VIC0VECTCNTL11 (VIC0_BASE+0x22C) /* R/W Vector control 11 register */#define VIC0VECTCNTL12 (VIC0_BASE+0x230) /* R/W Vector control 12 register */#define VIC0VECTCNTL13 (VIC0_BASE+0x234) /* R/W Vector control 13 register */#define VIC0VECTCNTL14 (VIC0_BASE+0x238) /* R/W Vector control 14 register */#define VIC0VECTCNTL15 (VIC0_BASE+0x23C) /* R/W Vector control 15 register */#define VIC0ITCR (VIC0_BASE+0x300) /* R/W Test control register */#define VIC0ITIP1 (VIC0_BASE+0x304) /* R Test input register (nVICIRQIN/nVICFIQIN) */#define VIC0ITIP2 (VIC0_BASE+0x308) /* R Test input register (VICVECTADDRIN) */#define VIC0ITOP1 (VIC0_BASE+0x30C) /* R Test output register (nVICIRQ/nVICFIQ) */#define VIC0ITOP2 (VIC0_BASE+0x310) /* R Test output register (VICVECTADDROUT) */#define VIC0PERIPHID0 (VIC0_BASE+0xFE0) /* R Peripheral ID register bits 7:0 */#define VIC0PERIPHID1 (VIC0_BASE+0xFE4) /* R Peripheral ID register bits 15:8 */#define VIC0PERIPHID2 (VIC0_BASE+0xFE8) /* R Peripheral ID register bits 23:16 */#define VIC0PERIPHID3 (VIC0_BASE+0xFEC) /* R Peripheral ID register bits 31:24 *//* 800C_0000 - 800C_FFFF: VIC 0 */#define VIC1_OFFSET 0x0C0000#define VIC1_BASE (EP93XX_AHB_BASE|VIC1_OFFSET)#define VIC1 (VIC1_BASE+0x000)#define VIC1IRQSTATUS (VIC1_BASE+0x000) /* R IRQ status register */#define VIC1FIQSTATUS (VIC1_BASE+0x004) /* R FIQ status register */#define VIC1RAWINTR (VIC1_BASE+0x008) /* R Raw interrupt status register */#define VIC1INTSELECT (VIC1_BASE+0x00C) /* R/W Interrupt select register */#define VIC1INTENABLE (VIC1_BASE+0x010) /* R/W Interrupt enable register */#define VIC1INTENCLEAR (VIC1_BASE+0x014) /* W Interrupt enable clear register */#define VIC1SOFTINT (VIC1_BASE+0x018) /* R/W Software interrupt register */#define VIC1SOFTINTCLEAR (VIC1_BASE+0x01C) /* R/W Software interrupt clear register */#define VIC1PROTECTION (VIC1_BASE+0x020) /* R/W Protection enable register */#define VIC1VECTADDR (VIC1_BASE+0x030) /* R/W Vector address register */#define VIC1DEFVECTADDR (VIC1_BASE+0x034) /* R/W Default vector address register */#define VIC1VECTADDR00 (VIC1_BASE+0x100) /* R/W Vector address 00 register */#define VIC1VECTADDR01 (VIC1_BASE+0x104) /* R/W Vector address 01 register */#define VIC1VECTADDR02 (VIC1_BASE+0x108) /* R/W Vector address 02 register */#define VIC1VECTADDR03 (VIC1_BASE+0x10C) /* R/W Vector address 03 register */#define VIC1VECTADDR04 (VIC1_BASE+0x110) /* R/W Vector address 04 register */#define VIC1VECTADDR05 (VIC1_BASE+0x114) /* R/W Vector address 05 register */#define VIC1VECTADDR06 (VIC1_BASE+0x118) /* R/W Vector address 06 register */#define VIC1VECTADDR07 (VIC1_BASE+0x11C) /* R/W Vector address 07 register */#define VIC1VECTADDR08 (VIC1_BASE+0x120) /* R/W Vector address 08 register */#define VIC1VECTADDR09 (VIC1_BASE+0x124) /* R/W Vector address 09 register */#define VIC1VECTADDR10 (VIC1_BASE+0x128) /* R/W Vector address 10 register */#define VIC1VECTADDR11 (VIC1_BASE+0x12C) /* R/W Vector address 11 register */#define VIC1VECTADDR12 (VIC1_BASE+0x130) /* R/W Vector address 12 register */#define VIC1VECTADDR13 (VIC1_BASE+0x134) /* R/W Vector address 13 register */#define VIC1VECTADDR14 (VIC1_BASE+0x138) /* R/W Vector address 14 register */#define VIC1VECTADDR15 (VIC1_BASE+0x13C) /* R/W Vector address 15 register */#define VIC1VECTCNTL00 (VIC1_BASE+0x200) /* R/W Vector control 00 register */#define VIC1VECTCNTL01 (VIC1_BASE+0x204) /* R/W Vector control 01 register */#define VIC1VECTCNTL02 (VIC1_BASE+0x208) /* R/W Vector control 02 register */#define VIC1VECTCNTL03 (VIC1_BASE+0x20C) /* R/W Vector control 03 register */#define VIC1VECTCNTL04 (VIC1_BASE+0x210) /* R/W Vector control 04 register */#define VIC1VECTCNTL05 (VIC1_BASE+0x214) /* R/W Vector control 05 register */#define VIC1VECTCNTL06 (VIC1_BASE+0x218) /* R/W Vector control 06 register */#define VIC1VECTCNTL07 (VIC1_BASE+0x21C) /* R/W Vector control 07 register */#define VIC1VECTCNTL08 (VIC1_BASE+0x220) /* R/W Vector control 08 register */#define VIC1VECTCNTL09 (VIC1_BASE+0x224) /* R/W Vector control 09 register */#define VIC1VECTCNTL10 (VIC1_BASE+0x228) /* R/W Vector control 10 register */#define VIC1VECTCNTL11 (VIC1_BASE+0x22C) /* R/W Vector control 11 register */#define VIC1VECTCNTL12 (VIC1_BASE+0x230) /* R/W Vector control 12 register */#define VIC1VECTCNTL13 (VIC1_BASE+0x234) /* R/W Vector control 13 register */#define VIC1VECTCNTL14 (VIC1_BASE+0x238) /* R/W Vector control 14 register */#define VIC1VECTCNTL15 (VIC1_BASE+0x23C) /* R/W Vector control 15 register */#define VIC1ITCR (VIC1_BASE+0x300) /* R/W Test control register */#define VIC1ITIP1 (VIC1_BASE+0x304) /* R Test input register (nVICIRQIN/nVICFIQIN) */#define VIC1ITIP2 (VIC1_BASE+0x308) /* R Test input register (VICVECTADDRIN) */#define VIC1ITOP1 (VIC1_BASE+0x30C) /* R Test output register (nVICIRQ/nVICFIQ) */#define VIC1ITOP2 (VIC1_BASE+0x310) /* R Test output register (VICVECTADDROUT) */#define VIC1PERIPHID0 (VIC1_BASE+0xFE0) /* R Peripheral ID register bits 7:0 */#define VIC1PERIPHID1 (VIC1_BASE+0xFE4) /* R Peripheral ID register bits 15:8 */#define VIC1PERIPHID2 (VIC1_BASE+0xFE8) /* R Peripheral ID register bits 23:16 */#define VIC1PERIPHID3 (VIC1_BASE+0xFEC) /* R Peripheral ID register bits 31:24 *//*800D_0000 - 807F_FFFF: Reserved AHB space *//******************************************************************//******************************************************************//* EP93xx APB Blocks Base Addrs *//* The APB address map is: *//* Start End Size Usage *//* 8080_0000 8080_FFFF: 64 K Reserved *//* 8081_0000 8081_FFFF: 64 K Timer control registers *//* 8082_0000 8082_FFFF: 64 K I2S control registers *//* 8083_0000 8083_FFFF: 64 K Reserved *//* 8084_0000 8084_FFFF: 64 K GPIO control registers *//* 8085_0000 8085_FFFF: 64 K Reserved *//* 8086_0000 8086_FFFF: 64 K Reserved *//* 8087_0000 8087_FFFF: 64 K Reserved *//* 8088_0000 8088_FFFF: 64 K AAC control registers *//* 8089_0000 8089_FFFF: 64 K Reserved *//* 808A_0000 808A_FFFF: 64 K SPI1 control registers *//* 808B_0000 808B_FFFF: 64 K IrDA control registers *//* 808C_0000 808C_FFFF: 64 K UART1 control registers *//* 808D_0000 808D_FFFF: 64 K UART2 control registers *//* 808E_0000 808E_FFFF: 64 K UART3 control registers *//* 808F_0000 808F_FFFF: 64 K Key Matrix control registers *//* 8090_0000 8090_FFFF: 64 K Touch Screen control registers *//* 8091_0000 8091_FFFF: 64 K PWM control registers *//* 8092_0000 8092_FFFF: 64 K Real Time Clock control registers *//* 8093_0000 8093_1FFF: 64 K Syscon control registers *//* 8093_2000 8093_FFFF: 64 K Security control registers *//* 8094_0000 8094_FFFF: 64 K Watchdog control registers *//* 8095_0000 8FFF_FFFF: 128M Reserved */#define EP93XX_APB_BASE (IO_BASE_PHYS | 0x00800000)/* 8080_0000 - 8080_ffff: Reserved *//* 8081_0000 - 8081_ffff: Timers */#define TIMERS_OFFSET 0x010000#define TIMERS_BASE (EP93XX_APB_BASE|TIMERS_OFFSET)#define TIMER1LOAD (TIMERS_BASE+0x00)#define TIMER1VALUE (TIMERS_BASE+0x04)#define TIMER1CONTROL (TIMERS_BASE+0x08)#define TIMER1CLEAR (TIMERS_BASE+0x0C)#define TIMER1TEST (TIMERS_BASE+0x10)#define TIMER2LOAD (TIMERS_BASE+0x20)#define TIMER2VALUE (TIMERS_BASE+0x24)#define TIMER2CONTROL (TIMERS_BASE+0x28)#define TIMER2CLEAR (TIMERS_BASE+0x2C)#define TIMER2TEST (TIMERS_BASE+0x30)#define TIMER3LOAD (TIMERS_BASE+0x80)#define TIMER3VALUE (TIMERS_BASE+0x84)#define TIMER3CONTROL (TIMERS_BASE+0x88)#define TIMER3CLEAR (TIMERS_BASE+0x8C)#define TIMER3TEST (TIMERS_BASE+0x90)#define TTIMERBZCONT (TIMERS_BASE+0x40)#define TIMER4VALUELOW (TIMERS_BASE+0x60)#define TIMER4VALUEHIGH (TIMERS_BASE+0x64)/* 8082_0000 - 8082_ffff: SAI (I2S) */#define SAI_OFFSET 0x020000#define SAI_BASE (EP93XX_APB_BASE|SAI_OFFSET)#define SAI (SAI_BASE+0x00)#define SAI_TX_CLK_CFG (SAI_BASE+0x00) /* 8082.0000 R/W Transmitter clock config register */#define SAI_RX_CLK_CFG (SAI_BASE+0x04) /* 8082.0004 R/W Receiver clock config register */#define SAI_CSR (SAI_BASE+0x08) /* 8082.0008 R/W SAI Global Status register. This */ /* reflects the status of the 3 RX */ /* FIFOs and the 3 TX FIFOs */#define SAI_GCR (SAI_BASE+0x0C) /* 8082.000C R/W SAI Global Control register */#define SAI_TX0_LEFT (SAI_BASE+0x10) /* 8082.0010 R/W Left TX data reg for channel 0 */#define SAI_TX0_RIGHT (SAI_BASE+0x14) /* 8082.0014 R/W Right TX data reg for channel 0 */#define SAI_TX1_LEFT (SAI_BASE+0x18) /* 8082.0018 R/W Left TX data reg for channel 1 */#define SAI_TX1_RIGHT (SAI_BASE+0x1C) /* 8082.001C R/W Right TX data reg for channel 1 */#define SAI_TX2_LEFT (SAI_BASE+0x20) /* 8082.0020 R/W Left TX data reg for channel 2 */#define SAI_TX2_RIGHT (SAI_BASE+0x24) /* 8082.0024 R/W Right TX data reg for channel 2 */#define SAI_TX_LCR (SAI_BASE+0x28) /* 8082.0028 R/W TX Line Control data register */#define SAI_TX_CR (SAI_BASE+0x2C) /* 8082.002C R/W TX Control register */#define SAI_TX_WL (SAI_BASE+0x30) /* 8082.0030 R/W TX Word Length */#define SAI_TX_EN0 (SAI_BASE+0x34) /* 8082.0034 R/W TX0 Channel Enable */#define SAI_TX_EN1 (SAI_BASE+0x38) /* 8082.0038 R/W TX1 Channel Enable */#define SAI_TX_EN2 (SAI_BASE+0x3C) /* 8082.003C R/W TX2 Channel Enable */#define SAI_RX0_LEFT (SAI_BASE+0x40) /* 8082.0040 R Left RX data reg for channel 0 */#define SAI_RX0_RIGHT (SAI_BASE+0x44) /* 8082.0044 R Right RX data reg for channel 0 */#define SAI_RX1_LEFT (SAI_BASE+0x48) /* 8082.0048 R Left RX data reg for channel 1 */#define SAI_RX1_RIGHT (SAI_BASE+0x4C) /* 8082.004c R Right RX data reg for channel 1 */#define SAI_RX2_LEFT (SAI_BASE+0x50) /* 8082.0050 R Left RX data reg for channel 2 */#define SAI_RX2_RIGHT (SAI_BASE+0x54) /* 8082.0054 R Right RX data reg for channel 2 */#define SAI_RX_LCR (SAI_BASE+0x58) /* 8082.0058 R/W RX Line Control data register */#define SAI_RX_CR (SAI_BASE+0x5C) /* 8082.005C R/W RX Control register */#define SAI_RX_WL (SAI_BASE+0x60) /* 8082.0060 R/W RX Word Length */#define SAI_RX_EN0 (SAI_BASE+0x64) /* 8082.0064 R/W RX0 Channel Enable */#define SAI_RX_EN1 (SAI_BASE+0x68) /* 8082.0068 R/W RX1 Channel Enable */#define SAI_RX_EN2 (SAI_BASE+0x6C) /* 8082.006C R/W RX2 Channel Enable *//* 8083_0000 - 8083_ffff: Security Block */#define SECURITY_OFFSET 0x030000#define SECURITY_BASE (EP93XX_APB_BASE|SECURITY_OFFSET)#define SECFLG (SECURITY_BASE+0x2400)#define SECEN (SECURITY_BASE+0x2410)#define UNIQID (SECURITY_BASE+0x2440)#define UNIQCHK (SECURITY_BASE+0x2450)#define UNIQVAL (SECURITY_BASE+0x2460)#define CLINBOOT (SECURITY_BASE+0x2480)#define CLINVADDR (SECURITY_BASE+0x2484)#define CLSETSKRNL (SECURITY_BASE+0x2488)#define CLSKRNL (SECURITY_BASE+0x248C)#define ITTMP (SECURITY_BASE+0x2490)#define ETBL1 (SECURITY_BASE+0x24A0)#define ETCL1 (SECURITY_BASE+0x24A4)#define ETAPL1 (SECURITY_BASE+0x24A8)#define ETSPTREG1 (SECURITY_BASE+0x24B0)#define ETSPTREG2 (SECURITY_BASE+0x24B4)#define ETSPTREG3 (SECURITY_BASE+0x24B8)#define SECID1 (SECURITY_BASE+0x2500)#define SECID2 (SECURITY_BASE+0x2504)#define SECCHK1 (SECURITY_BASE+0x2520)#define SECCHK2 (SECURITY_BASE+0x2524)#define SECVAL1 (SECURITY_BASE+0x2540)#define SECVAL2 (SECURITY_BASE+0x2544)#define UNIQID2 (SECURITY_BASE+0x2700)#define UNIQID3 (SECURITY_BASE+0x2704)#define UNIQID4 (SECURITY_BASE+0x2708)#define UNIQID5 (SECURITY_BASE+0x270C)#define UNIQCHK2 (SECURITY_BASE+0x2710)#define USRFLG (SECURITY_BASE+0x2714)#define UNIQVAL2 (SECURITY_BASE+0x2720)#define UNIQVAL3 (SECURITY_BASE+0x2724)#define UNIQVAL4 (SECURITY_BASE+0x2728)#define TESTVAL (SECURITY_BASE+0x2744)#define TESTCHK (SECURITY_BASE+0x2754)#define ACHK1 (SECURITY_BASE+0x27A0)#define ACHK2 (SECURITY_BASE+0x27A4)#define PROCRESET (SECURITY_BASE+0x27A8)⌨️ 快捷键说明
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