clps9312.h

SkyEye是一个可以运行嵌入式操作系统的硬件仿真工具

///#define VLINESTOTAL             (RASTER_BASE+0x00)
///#define VSYNCSTRTSTOP           (RASTER_BASE+0x04)
///#define VACTIVESTRTSTOP         (RASTER_BASE+0x08)
///#define VCLKSTRTSTOP            (RASTER_BASE+0x0C)
///#define HCLKSTOTAL              (RASTER_BASE+0x10)
///#define HSYNCSTRTSTOP           (RASTER_BASE+0x14)
///#define HACTIVESTRTSTOP         (RASTER_BASE+0x18)
///#define HCLKSTRTSTOP            (RASTER_BASE+0x1C)
///#define BRIGHTNESS              (RASTER_BASE+0x20)
///#define VIDEOATTRIBS            (RASTER_BASE+0x24)
///#define VIDSCRNPAGE             (RASTER_BASE+0x28)
///#define VIDSCRNHPG              (RASTER_BASE+0x2C)
///#define SCRNLINES               (RASTER_BASE+0x30)
///#define LINELENGTH              (RASTER_BASE+0x34)
///#define VLINESTEP               (RASTER_BASE+0x38)
///#define LINECARRY               (RASTER_BASE+0x3C)
///#define BLINKRATE               (RASTER_BASE+0x40)
///#define BLINKMASK               (RASTER_BASE+0x44)
///#define BLINKPATTRN             (RASTER_BASE+0x48)
///#define PATTRNMASK              (RASTER_BASE+0x4C)
///#define BG_OFFSET               (RASTER_BASE+0x50)
///#define PIXELMODE               (RASTER_BASE+0x54)
///#define PARLLIFOUT              (RASTER_BASE+0x58)
///#define PARLLIFIN               (RASTER_BASE+0x5C)
///#define CURSOR_ADR_START        (RASTER_BASE+0x60)
///#define CURSOR_ADR_RESET        (RASTER_BASE+0x64)
///#define CURSORSIZE              (RASTER_BASE+0x68)
///#define CURSORCOLOR1            (RASTER_BASE+0x6C)
///#define CURSORCOLOR2            (RASTER_BASE+0x70)
///#define CURSORXYLOC             (RASTER_BASE+0x74)
///#define CURSOR_DHSCAN_LH_YLOC   (RASTER_BASE+0x78)
///#define REALITI_SWLOCK          (RASTER_BASE+0x7C)
///#define GS_LUT                  (RASTER_BASE+0x80)
///#define REALITI_TCR             (RASTER_BASE+0x100)
///#define REALITI_TISRA           (RASTER_BASE+0x104)
///#define REALITI_TISRB           (RASTER_BASE+0x108)
///#define CURSOR_TISR             (RASTER_BASE+0x10C)
///#define REALITI_TOCRA           (RASTER_BASE+0x110)
///#define REALITI_TOCRB           (RASTER_BASE+0x114)
///#define FIFO_TOCRA              (RASTER_BASE+0x118)
///#define FIFO_TOCRB              (RASTER_BASE+0x11C)
///#define BLINK_TISR              (RASTER_BASE+0x120)
///#define DAC_TISRA               (RASTER_BASE+0x124)
///#define DAC_TISRB               (RASTER_BASE+0x128)
///#define SHIFT_TISR              (RASTER_BASE+0x12C)
///#define DACMUX_TOCRA            (RASTER_BASE+0x130)
///#define DACMUX_TOCRB            (RASTER_BASE+0x134)
///#define PELMUX_TOCR             (RASTER_BASE+0x138)
///#define VIDEO_TOCRA             (RASTER_BASE+0x13C)
///#define VIDEO_TOCRB             (RASTER_BASE+0x140)
///#define YCRCB_TOCR              (RASTER_BASE+0x144)
///#define CURSOR_TOCR             (RASTER_BASE+0x148)
///#define VIDEO_TOCRC             (RASTER_BASE+0x14C)
///#define SHIFT_TOCR              (RASTER_BASE+0x150)
///#define BLINK_TOCR              (RASTER_BASE+0x154)
///#define REALITI_TCER            (RASTER_BASE+0x180)
///#define SIGVAL                  (RASTER_BASE+0x200)
///#define SIGCTL                  (RASTER_BASE+0x204)
///#define VSIGSTRTSTOP            (RASTER_BASE+0x208)
///#define HSIGSTRTSTOP            (RASTER_BASE+0x20C)
///#define SIGCLR                  (RASTER_BASE+0x210)
///#define ACRATE                  (RASTER_BASE+0x214)
///#define LUTCONT                 (RASTER_BASE+0x218)
///#define VBLANKSTRTSTOP          (RASTER_BASE+0x228)
///#define HBLANKSTRTSTOP          (RASTER_BASE+0x22C)
///#define LUT                     (RASTER_BASE+0x400)
///#define CURSORBLINK1            (RASTER_BASE+0x21C)
///#define CURSORBLINK2            (RASTER_BASE+0x220)
///#define CURSORBLINK             (RASTER_BASE+0x224)
///#define EOLOFFSET               (RASTER_BASE+0x230)
///#define FIFOLEVEL               (RASTER_BASE+0x234)
///#define GS_LUT2                 (RASTER_BASE+0x280)
///#define GS_LUT3                 (RASTER_BASE+0x300)

/* 8004_0000 - 8004_ffff: Graphics */
#define GRAPHICS_OFFSET         0x040000
#define GRAPHICS_BASE           (EP93XX_AHB_BASE|GRAPHICS_OFFSET)
///#define SRCPIXELSTRT            (GRAPHICS_BASE+0x00)
///#define DESTPIXELSTRT           (GRAPHICS_BASE+0x04)
///#define BLKSRCSTRT              (GRAPHICS_BASE+0x08)
///#define BLKDSTSTRT              (GRAPHICS_BASE+0x0C)
///#define BLKSRCWIDTH             (GRAPHICS_BASE+0x10)
///#define SRCLINELENGTH           (GRAPHICS_BASE+0x14)
///#define BLKDESTWIDTH            (GRAPHICS_BASE+0x18)
///#define BLKDESTHEIGHT           (GRAPHICS_BASE+0x1C)
///#define DESTLINELENGTH          (GRAPHICS_BASE+0x20)
///#define BLOCKCTRL               (GRAPHICS_BASE+0x24)
///#define TRANSPATTRN             (GRAPHICS_BASE+0x28)
///#define BLOCKMASK               (GRAPHICS_BASE+0x2C)
///#define BACKGROUND              (GRAPHICS_BASE+0x30)
///#define LINEINC                 (GRAPHICS_BASE+0x34)
///#define LINEINIT                (GRAPHICS_BASE+0x38)
///#define LINEPATTRN              (GRAPHICS_BASE+0x3C)
///#define GOATTCR                 (GRAPHICS_BASE+0x40)
///#define GOATTISRA               (GRAPHICS_BASE+0x44)
///#define GOATTISRB               (GRAPHICS_BASE+0x48)
///#define GOATTOCRA               (GRAPHICS_BASE+0x4C)
///#define GOATTOCRB               (GRAPHICS_BASE+0x50)
///#define GOATTOCRC               (GRAPHICS_BASE+0x54) 
///#define GOATTCER                (GRAPHICS_BASE+0x80)

/* 8005_0000 - 8005_ffff: Reserved  */

/*8006_0000 - 8006_ffff: SDRAM  */
#define SDRAM_OFFSET            0x060000
#define SDRAM_BASE              (EP93XX_AHB_BASE|SDRAM_OFFSET)
//#define SDRAMRESERVED         (SDRAM_BASE+0x00) /* Reserved */
#define SDRAMGLOBALCFG          (SDRAM_BASE+0x04)
#define SDRAMREFRESHTIME        (SDRAM_BASE+0x08)	/* Refresh Timer */
#define SDRAMBOOTSTATUS         (SDRAM_BASE+0x0C)
#define SDRAMCFG0               (SDRAM_BASE+0x10)	/* Configuration Register 0 (nSDCS0) */
#define SDRAMCFG1               (SDRAM_BASE+0x14)	/* Configuration Register 1 (nSDCS1) */
#define SDRAMCFG2               (SDRAM_BASE+0x18)	/* Configuration Register 2 (nSDCS2) */
#define SDRAMCFG3               (SDRAM_BASE+0x1C)	/* Configuration Register 3 (nSDCS3) */

/* 8007_0000 - 8007_ffff: ARM920T Slave  */

/* 8008_0000 - 8008_ffff: SRAM CS */

/* SMC register map                                                            */
/* Address     Read Location                   Write Location                  */
/* 0x8000.2000 SMCBCR0(Bank config register 0) SMCBCR0(Bank config register 0) */
/* 0x8000.2004 SMCBCR1(Bank config register 1) SMCBCR1(Bank config register 1) */
/* 0x8000.2008 SMCBCR2(Bank config register 2) SMCBCR2(Bank config register 2) */
/* 0x8000.200C SMCBCR3(Bank config register 3) SMCBCR3(Bank config register 3) */
/* 0x8000.2010 Reserved, RAZ Reserved, RAZ                                     */
/* 0x8000.2014 Reserved, RAZ Reserved, RAZ                                     */
/* 0x8000.2018 SMCBCR6(Bank config register 6) SMCBCR6(Bank config register 6) */
/* 0x8000.201C SMCBCR7(Bank config register 7) SMCBCR7(Bank config register 7) */
/* 0x8000.2020 PC1Attribute Register PC1Attribute                              */
/* 0x8000.2024 PC1Common Register PC1Common                                    */
/* 0x8000.2028 PC1IO Register PC1IO                                            */
/* 0x8000.202C Reserved, RAZ Reserved, RAZ                                     */
/* 0x8000.2030 PC2Attribute Register PC2Attribute                              */
/* 0x8000.2034 PC2Common Register PC2Common                                    */
/* 0x8000.2038 PC2IO Register PC2IO                                            */
/* 0x8000.203C Reserved, RAZ Reserved, RAZ                                     */
/* 0x8000.2040 PCMCIA control register PCMCIA control register                 */

#define SRAM_OFFSET             0x080000
#define SRAM_BASE               (EP93XX_AHB_BASE|SRAM_OFFSET)
#define SMCBCR0                 (SRAM_BASE+0x00)	/* 0x8000.2000  Bank config register 0 */
#define SMCBCR1                 (SRAM_BASE+0x04)	/* 0x8000.2004  Bank config register 1 */
#define SMCBCR2                 (SRAM_BASE+0x08)	/* 0x8000.2008  Bank config register 2 */
#define SMCBCR3                 (SRAM_BASE+0x0C)	/* 0x8000.200C  Bank config register 3 */
  /* 0x8000.2010  Reserved, RAZ          */
  /* 0x8000.2014  Reserved, RAZ          */
#define SMCBCR6                 (SRAM_BASE+0x18)	/* 0x8000.2018  Bank config register 6 */
#define SMCBCR7                 (SRAM_BASE+0x1C)	/* 0x8000.201C  Bank config register 7 */
#define PC1ATTRIB               (SRAM_BASE+0x20)	/* 0x8000.2020  PC1 Attribute Register */
#define PC1COMMON               (SRAM_BASE+0x24)	/* 0x8000.2024  PC1 Common Register    */
#define PC1IO                   (SRAM_BASE+0x28)	/* 0x8000.2028  PC1 IO Register        */
  /* 0x8000.202C Reserved, RAZ           */
#define PC2ATTRIB               (SRAM_BASE+0x30)	/* 0x8000.2030 PC2 Attribute Register   */
#define PC2COMMON               (SRAM_BASE+0x34)	/* 0x8000.2034 PC2 Common Register     */
#define PC2IO                   (SRAM_BASE+0x38)	/* 0x8000.2038 PC2 IO Register         */
  /* 0x8000.203C Reserved, RAZ           */
#define PCMCIACNT               (SRAM_BASE+0x40)	/* 0x8000.2040 PCMCIA control register */

/* 8009_0000 - 8009_ffff: Boot ROM (Remap low or high) */
/*   0000 - 8009_0FFF - Boot ROM code                  */
/*   0FFF - 8009_FFFF - Reserved                       */
#define BOOT_OFFSET             0x090000
#define BOOT_BASE               (EP93XX_AHB_BASE|BOOT_OFFSET)
#define BOOT                    (BOOT_BASE+0x00)

/* 800A_0000 - 800A_ffff: IDE Interface  */
#define IDE_OFFSET              0x0a0000
#define IDE_BASE                (EP93XX_AHB_BASE|IDE_OFFSET)
///#define IDECR                   (IDE_BASE+0x00)
///#define IDECFG                  (IDE_BASE+0x04)
///#define IDEMDMAOP               (IDE_BASE+0x08)
///#define IDEUDMAOP               (IDE_BASE+0x0C)
///#define IDEDATAOUT              (IDE_BASE+0x10)
///#define IDEDATAIN               (IDE_BASE+0x14)
///#define IDEMDMADATAOUT          (IDE_BASE+0x18)
///#define IDEMDMADATAIN           (IDE_BASE+0x1C)
///#define IDEUDMADATAOUT          (IDE_BASE+0x20)
///#define IDEUDMADATAIN           (IDE_BASE+0x24)
///#define IDEUDMASTATUS           (IDE_BASE+0x28)
///#define IDEUDMADEBUG            (IDE_BASE+0x2C)
///#define IDEUDMAWFST             (IDE_BASE+0x30)
///#define IDEUDMARFST             (IDE_BASE+0x34)

/* 800B_0000 - 800B_FFFF: VIC 0 */
#define VIC0_OFFSET              0x0B0000
#define VIC0_BASE                (EP93XX_AHB_BASE|VIC0_OFFSET)
#define VIC0                     (VIC0_BASE+0x000)
#define VIC0IRQSTATUS            (VIC0_BASE+0x000)	/* R   IRQ status register               */
#define VIC0FIQSTATUS            (VIC0_BASE+0x004)	/* R   FIQ status register               */
#define VIC0RAWINTR              (VIC0_BASE+0x008)	/* R   Raw interrupt status register     */
#define VIC0INTSELECT            (VIC0_BASE+0x00C)	/* R/W Interrupt select register         */
#define VIC0INTENABLE            (VIC0_BASE+0x010)	/* R/W Interrupt enable register         */
#define VIC0INTENCLEAR           (VIC0_BASE+0x014)	/* W   Interrupt enable clear register   */
#define VIC0SOFTINT              (VIC0_BASE+0x018)	/* R/W Software interrupt register       */
#define VIC0SOFTINTCLEAR         (VIC0_BASE+0x01C)	/* R/W Software interrupt clear register */
#define VIC0PROTECTION           (VIC0_BASE+0x020)	/* R/W Protection enable register        */
#define VIC0VECTADDR             (VIC0_BASE+0x030)	/* R/W Vector address register           */
#define VIC0DEFVECTADDR          (VIC0_BASE+0x034)	/* R/W Default vector address register   */
#define VIC0VECTADDR00           (VIC0_BASE+0x100)	/* R/W Vector address 00 register        */
#define VIC0VECTADDR01           (VIC0_BASE+0x104)	/* R/W Vector address 01 register        */
#define VIC0VECTADDR02           (VIC0_BASE+0x108)	/* R/W Vector address 02 register        */
#define VIC0VECTADDR03           (VIC0_BASE+0x10C)	/* R/W Vector address 03 register        */
#define VIC0VECTADDR04           (VIC0_BASE+0x110)	/* R/W Vector address 04 register        */
#define VIC0VECTADDR05           (VIC0_BASE+0x114)	/* R/W Vector address 05 register        */
#define VIC0VECTADDR06           (VIC0_BASE+0x118)	/* R/W Vector address 06 register        */
#define VIC0VECTADDR07           (VIC0_BASE+0x11C)	/* R/W Vector address 07 register        */
#define VIC0VECTADDR08           (VIC0_BASE+0x120)	/* R/W Vector address 08 register        */
#define VIC0VECTADDR09           (VIC0_BASE+0x124)	/* R/W Vector address 09 register        */
#define VIC0VECTADDR10           (VIC0_BASE+0x128)	/* R/W Vector address 10 register        */
#define VIC0VECTADDR11           (VIC0_BASE+0x12C)	/* R/W Vector address 11 register        */
#define VIC0VECTADDR12           (VIC0_BASE+0x130)	/* R/W Vector address 12 register        */
#define VIC0VECTADDR13           (VIC0_BASE+0x134)	/* R/W Vector address 13 register        */
#define VIC0VECTADDR14           (VIC0_BASE+0x138)	/* R/W Vector address 14 register        */
#define VIC0VECTADDR15           (VIC0_BASE+0x13C)	/* R/W Vector address 15 register        */
#define VIC0VECTCNTL00           (VIC0_BASE+0x200)	/* R/W Vector control 00 register        */
#define VIC0VECTCNTL01           (VIC0_BASE+0x204)	/* R/W Vector control 01 register        */
#define VIC0VECTCNTL02           (VIC0_BASE+0x208)	/* R/W Vector control 02 register        */