skyeye_mach_at91.c

SkyEye是一个可以运行嵌入式操作系统的硬件仿真工具

		rpr = data;
		break;
	case 0xe:		// TPR
		tx_buf = data;
		break;
	case 0xf:		// TCR
		for (; tx_buf && data > 0; data--) {
			char c = mem_read_char (state, tx_buf++);

			/* 2007-01-18 modified by Anthony Lee : for new uart device frame */
			skyeye_uart_write(-1, &c, 1, NULL);

			//printf("%c", mem_read_char(state, tx_buf++));
			//fflush(stdout);
		}
		tx_buf = 0;
		break;
	default:
		fprintf(stderr, "IO erro in %s\n", __FUNCTION__);
		skyeye_exit(-1);
	}
}

static ARMword timer_read(int index, ARMul_State * state, int offset){
	ARMword data;
	at91_timer_t * timer = &io.tc_channel[index];
	switch(offset){
	case 0x0:	/* TIMER 1 CCR */
		data = timer->ccr; 
		
		break;
	case 0x4:	/* TIMER 1 CMR */
		data = timer->cmr;
		break;
	case 0x10:	/* TIMER 1 CV */
		data = timer->cv;
		data = io.tcd[0];
		break;
	case 0x14:      /* TIMER 1 RA */
		data = timer->ra;
                break;
	case 0x18:      /* TIMER 1 RB */
                data = timer->rb;
                break;

	case 0x1c:	/* TIMER 1 RC */
		data = timer->rc;
		break;
	case 0x20:	/* TIMER 1 SR */
		data = timer->sr;
		if(timer->sr & 0x10)
			timer->sr &= ~0x10;
		//fprintf(stderr, "timer %d read sr,data=0x%x\n",index, data);
		//io.ipr &= ~(1<<IRQ_TC1);
		break;
	case 0x24:	/* TIMER 1 IER */
		data = timer->ier;
		break;
	case 0x28:	/* TIMER 1 IDR */
		data = timer->idr;
		break;
        case 0x2C:      /* TIMER 1 IMR */
                data = timer->imr;
                break;

	default:
		fprintf(stderr, "IO erro in %s, offset=0x%x\n", __FUNCTION__, offset);
                //skyeye_exit(-1);
	}
	return data;
}
static void timer_write(int index, ARMul_State * state, int offset, ARMword data){
	at91_timer_t * timer = &io.tc_channel[index];
	switch(offset){
	case 0x0:	/* TIMER 1 CCR */
		timer->ccr = data; 
		if (data & 0x2) {
                        io.syscon &= ~TC1M;
                }
                else {
                        io.syscon |= TC1M;
                }

		
		break;
	case 0x4:	/* TIMER 1 CMR */
		timer->cmr = data;
		break;
	case 0x10:	/* TIMER 1 CV */
		timer->cv = data ;
		io.tcd[0] = io.tcd_reload[0] = data & 0xffff;
		break;
	case 0x14:      /* TIMER 1 RA */
		timer->ra = data;
                break;
	case 0x18:      /* TIMER 1 RB */
                timer->rb = data;
                break;

	case 0x1c:	/* TIMER 1 RC */
		timer->rc = data;
		io.tcd[0] = io.tcd_reload[0] = data & 0xffff;
		break;
	case 0x20:	/* TIMER 1 SR */
		timer->sr = data;
		//io.ipr &= ~(1<<IRQ_TC1);
		break;
	case 0x24:	/* TIMER 1 IER */
		timer->ier = data;
		break;
	case 0x28:	/* TIMER 1 IDR */
		timer->idr = data;
		break;
        case 0x2C:      /* TIMER 1 IMR */
                timer->imr = data;
                break;

	default:
		fprintf(stderr, "IO erro in %s ,addr=0x%x\n", __FUNCTION__, offset);
                //skyeye_exit(-1);
	}
}

static ARMword
at91_io_read_byte (ARMul_State * state, ARMword addr)
{
	fprintf(stderr, "IO erro in %s, addr=0x%x\n", __FUNCTION__,addr);
	return 0;
}

ARMword
at91_io_read_halfword (ARMul_State * state, ARMword addr)
{
	fprintf(stderr, "IO erro in %s\n", __FUNCTION__);
	return 0;
}

ARMword
at91_io_read_word (ARMul_State * state, ARMword addr)
{

	ARMword data = -1;
	int i;
	ARMword ts_addr;
	ts_addr = addr & ~3;	// 1 word==4 byte
	if (ts_addr >= io.ts_addr_begin && ts_addr <= io.ts_addr_end) {
		data = io.ts_buffer[(ts_addr - io.ts_addr_begin) / 4];
		return data;
	}

	switch (addr) {
	case 0xfffff100:	/* IVR */
		data = io.ipr;
		DBG_PRINT ("IVR irqs=%x ", data);
		for (i = 0; i < 32; i++)
			if (data & (1 << i))
				break;
		if (i < 32) {
			data = i;
			io.ipr &= ~(1 << data);
			at91_update_int (state);
		}
		else
			data = 0;
		io.ivr = data;
		//current_ivr = data;
		DBG_PRINT ("read IVR=%d\n", data);
		break;
	case 0xfffff108:	/* interrupt status register */
		//      data = current_ivr;
		data = io.ivr;
		break;
	case 0xfffff110:	/* IMR */
		data = io.imr;
		break;
	case 0xfffff114:	/* CORE interrupt status register */
		data = io.cisr;
		data = io.imr;
		break;
	case 0xfffff120:	/* IECR */
		data = io.iecr;
		data = io.imr;
		break;
	case 0xfffff124:	/* IDCR */
		break;
	case 0xfff00000:	/* CPU ID */
		data = 0x2078aa0;
		data = 0x14000040;
		break;
	case 0xfffe00c0:	/* TIMER 1 BCR */
		DBG_PRINT ("T1-BCR io_read_word(0x%08x) = 0x%08x\n", addr,
			   data);
		break;
	case 0xfffe00c4:	/* TIMER 1 BMR */
		DBG_PRINT ("T1-BMR io_read_word(0x%08x) = 0x%08x\n", addr,
			   data);
		break;
	default:
		if ((addr & 0xffffff00) == 0xfffff000)
			break;
		if ((addr & 0xfffff000) == 0xfffd0000) {
			return uart_read (state, addr);
		}
		if ((addr & 0xfffff000) == 0xfffcc000) {
			//return uart_read (state, addr);
			break;
		}
		if(addr >= 0xfffe0000 && addr < 0xfffe00c0){
			return timer_read(((addr & 0xc0) >> 6), state, (addr & 0x3f));
		}
		//fprintf (stderr,
		//       "NumInstr %llu, io_read_word unknown addr(0x%08x) = 0x%08x\n",
		//       state->NumInstrs, addr, data);
		//SKYEYE_OUTREGS (stderr);
		//ARMul_Debug(state, 0, 0);
		break;
	}
	return data;
}

void
at91_io_write_byte (ARMul_State * state, ARMword addr, ARMword data)
{
	fprintf(stderr," IO error in %s,addr=0x%x\n", __FUNCTION__);
	return;
}

void
at91_io_write_halfword (ARMul_State * state, ARMword addr, ARMword data)
{
	fprintf(stderr," IO error in %s\n", __FUNCTION__);
	return;
}

void
at91_io_write_word (ARMul_State * state, ARMword addr, ARMword data)
{
	/*
	 * The Atmel system registers
	 */
	if(addr >= 0xfffe0000 && addr < 0xfffe00c0){
        	timer_write((addr & 0xc0), state, (addr & 0x3f), data);
		return;
        }

	switch (addr) {
	case 0xfffff108:	/* ISR */
		//DBG_PRINT("write ISR=0x%x\n", data);
		//io.isr = data;
		break;
	case 0xfffff110:	/* IMR */
		//io.imr = data;
		break;
	case 0xfffff114:	/* CORE interrupt status register */
		//io.cisr = data;
		DBG_PRINT ("write CISR=0x%x\n", data);
		break;
	case 0xfffff120:	/* IECR */
		DBG_PRINT ("IECR=0x%x\n", data);
		io.iecr = data;
		io.imr |= data;
		break;
	case 0xfffff124:	/* IDCR */
		DBG_PRINT ("IDCR=0x%x\n", data);
		io.idcr = data;
		io.imr &= ~data;
		break;
	case 0xfffff128:	/* CLEAR interrupts */
		DBG_PRINT ("ICCR=0x%x\n", data);
		io.iccr = data;
		io.ipr &= ~data;
		break;
	case 0xfffff130:	/* EOI */
		DBG_PRINT (stderr, "EOI=0x%x\n", data);
               /**
                * 2.4.32 in uClinux is broken somehow and always sends
                * 0xfffff130 as both address and data, sometimes clearing
                * not yet processed interrupt. Anyway, the thing
                * works without the following
               */
#if 0
		io.eoicr = data;
		io.ipr &= ~data;
#endif
		at91_update_int (state);
		break;
	case 0xfff00000:	/* CPU ID */
		break;
	case 0xfffe00c0:	/* TIMER 1 BCR */
		DBG_PRINT ("T1-BCR io_write_word(0x%08x) = 0x%08x\n", addr,
			   data);
		break;
	case 0xfffe00c4:	/* TIMER 1 BMR */
		DBG_PRINT ("T1-BMR io_write_word(0x%08x) = 0x%08x\n", addr,
			   data);
		break;
	default:
		if ((addr & 0xfffff000) == 0xfffd0000) {
			uart_write (state, addr, data);
			break;
		}
		if ((addr & 0xfffff000) == 0xfffcc000) {
			//uart_write (state, addr, data);
			break;
		}
		if ((addr & 0xffffff00) == 0xfffff000)
			break;
		if ((addr & 0xffff0000) == 0xffff0000) {
			DBG_PRINT ("io_write_word(0x%08x) = 0x%08x\n", addr,
				   data);
			break;
		}
		//DBG_PRINT("io_write_word(0x%08x) = 0x%08x\n", addr, data);
		//fprintf (stderr,
		//       "NumInstr %llu,io_write_word unknown addr(0x%08x) = 0x%08x\n",
		//       state->NumInstrs, addr, data);
		//SKYEYE_OUTREGS (stderr);
		//ARMul_Debug(state, 0, 0);
		break;
	}
}

void
at91_mach_init (void * curr_state, machine_config_t * this_mach)
{
	ARMul_State *state = (ARMul_State *)curr_state;
	//chy 2003-08-19, setprocessor
	ARMul_SelectProcessor (state, ARM_v4_Prop);
	//chy 2004-05-09, set lateabtSig
	state->lateabtSig = HIGH;

	this_mach->mach_io_do_cycle = at91_io_do_cycle;
	this_mach->mach_io_reset = at91_io_reset;
	this_mach->mach_io_read_byte = at91_io_read_byte;
	this_mach->mach_io_write_byte = at91_io_write_byte;
	this_mach->mach_io_read_halfword = at91_io_read_halfword;
	this_mach->mach_io_write_halfword = at91_io_write_halfword;
	this_mach->mach_io_read_word = at91_io_read_word;
	this_mach->mach_io_write_word = at91_io_write_word;

	this_mach->mach_update_int = at91_update_int;

	this_mach->mach_set_intr = at91_set_intr;
	this_mach->mach_pending_intr = at91_pending_intr;
	this_mach->mach_update_intr = at91_update_intr;

	this_mach->mach_mem_read_byte = at91_mem_read_byte;
	this_mach->mach_mem_write_byte = at91_mem_write_byte;

	this_mach->state = (void *) state;

}