skyeye_mach_lpc2210.c

SkyEye是一个可以运行嵌入式操作系统的硬件仿真工具

	case 0xe0004000:
		data = io.timer[0].ir;
		break;
	case 0xe0004004:
		data = io.timer[0].tcr;
		break;
	case 0xe0004008:
		data = io.timer[0].tc;
		//io.vic.RawIntr &= ~IRQ_TC0;
		//printf("SKYEYE:Clear TC Interrupt,tc=%x,RawIntr=%x,\n",data,io.vic.RawIntr);
		//lpc2210_update_int(state);
		break;
	case 0xe000400c:
		data = io.timer[0].pr;
		break;
	case 0xe0004010:
		data = io.timer[0].pc;		
		break;
	case 0xe0004014:
		 data = io.timer[0].mcr;		
		break;
	case 0xe0004018:
		 data = io.timer[0].mr0;		
		break;

	/*pll*/
	case 0xe01fc080:
		data = io.pll.con;
		break;
	case 0xe01fc084:
		data = io.pll.cfg;
		break;
	case 0xe01fc088:
		data = io.pll.stat|1<<10; /*skyeye should aways return a pll ready*/
		break;
	case 0xe01fc08c:
		data = io.pll.feed;
		
	/*Pin Select Control*/
	case 0xe002c000:
		data = io.pinsel0;
		break;
	case 0xE002C004:
		data = io.pinsel1;
		break;
	case 0xE002C014:
		data = io.pinsel2;
		break;
	
	/*Extend Mem control*/
	case 0xFFE00000:
		data = io.bcfg[0];
		break;
	case 0xFFE00004:
		data = io.bcfg[1];
		break;
	case 0xFFE00008:
		data = io.bcfg[2];
		break;
	case 0xFFE0000c:
		data = io.bcfg[3];
		break;
	
	/*VIBDIV*/
	case 0xe01fc100:
		data = io.vibdiv;
		break;
	
	/*Real timer*/
	case 0xe0024080:
		data = io.preint;
		break;
	case 0xe0024084:
		data = io.prefrac;
		break;
	case 0xe0024008:
		data = io.ccr;
		break;
	case 0xe0024020:
		data = io.sec;
		break;
	case 0xe0024024:
		data = io.min;
		break;
	case 0xe0024028:
		data = io.hour;
		break;
	case 0xe002402c:
		data = io.dom;
		break;
	case 0xe0024030:
		data = io.dow;
		break;
	case 0xe0024034:
		data = io.doy;
		break;
	case 0xe0024038:
		data = io.month;
		break;
	case 0xe002403c:
		data = io.year;
		break;
	
	/*Mem accelerator regs*/
	case 0xe01fc000:
		data = io.mamcr;
		break;
	case 0xe01fc004:
		data = io.mamtim;
		break;
	
		
	default:
		if (addr >=0xe000c000 && addr <= 0xe000c01c) {
			data = lpc2210_uart_read(state, addr,0);
			break;
		}
		if (addr >=0xe0001000 && addr <= 0xe000101c) {
			data = lpc2210_uart_read(state, addr,1);
			break;
		}
		if(addr-0xfffff100 <=0x3c && addr-0xfffff100 >=0){
			data = io.vic.VectAddr[(addr-0xfffff100)/4] ;
			break;
		}
		if(addr-0xfffff200 <=0x3c && addr-0xfffff200>=0){
			data = io.vic.VectCntl[(addr-0xfffff200)/4] ;
			break;
		}
		
		printf("ERROR:io_read: addr = %x\n", addr);
		
		/*fprintf(stderr,"NumInstr %llu, io_read_word unknown addr(0x%08x) = 0x%08x\n", state->NumInstrs, addr, data);*/
		SKYEYE_OUTREGS(stderr);
		//ARMul_Debug(state, 0, 0);
		break;
	}
	return data; 													
}

ARMword lpc2210_io_read_byte(ARMul_State *state, ARMword addr)
{
			return lpc2210_io_read_word(state,addr);		
//			SKYEYE_OUTREGS(stderr);
			//exit(-1);
		
}

ARMword lpc2210_io_read_halfword(ARMul_State *state, ARMword addr)
{
		return lpc2210_io_read_word(state,addr);
		//SKYEYE_OUTREGS(stderr);
		//exit(-1);
}




void lpc2210_io_write_byte(ARMul_State *state, ARMword addr, ARMword data)
{

     lpc2210_io_write_word(state,addr,data);
	   //SKYEYE_OUTREGS(stderr);
	   //exit(-1);
         
}

void lpc2210_io_write_halfword(ARMul_State *state, ARMword addr, ARMword data)
{
	lpc2210_io_write_word(state,addr,data);
	//SKYEYE_OUTREGS(stderr);
	//exit(-1);
}

void lpc2210_io_write_word(ARMul_State *state, ARMword addr, ARMword data)
{
  	int i, mask, nIRQNum, nHighestIRQ;
	
	/*
  	 * The lpc2210 system registers
  	 */
	

	switch (addr) {
	case 0xfffff000: /* ISR */
		DBG_PRINT("SKYEYE:can not write  ISR,it is RO,=%d\n", data);
		break;
	case 0xfffff004: /* interrupt status register */
		//io.vic.FIQStatus = data ;
//		DBG_PRINT("read ISR=%x,%x\n", data, io.intsr);
		DBG_PRINT("can not write  FIQStatus,it is RO,=%d\n", data);
		break;
	case 0xfffff008: /* IMR */
		 //io.vic.RawIntr = data;
		 DBG_PRINT("can not write  RawIntr,it is RO,=%d\n", data);
		break;
	case 0xfffff00c: /* CORE interrupt status register */
		io.vic.IntSelect = data;
		break;
	case 0xfffff010: /* IER */
		io.vic.IntEnable = data;
		io.vic.IntEnClr = ~data;
		lpc2210_update_int(state);
//		data = unfix_int(io.intmr);
		DBG_PRINT("write IER=%x,after update IntEnable=%x\n", data,io.vic.IntEnable);
		break;
	case 0xfffff014: /* IECR */
		io.vic.IntEnClr = data;		
		io.vic.IntEnable = ~data;
		lpc2210_update_int(state);
		break;		

	case 0xfffff018: /* SIR */
		io.vic.SoftInt = data;
		break;	
	case 0xfffff01c: /* SICR */
		io.vic.SoftIntClear = data;
		break;	
	case 0xfffff020: /* PER */
		io.vic.Protection = data;
		break;	
	case 0xfffff030: /* VAR */
		//io.vic.Vect_Addr = data;
		//rmk by linxz, write VAR with any data will clear current int states
		//FIQ interrupt
		//FIXME:clear all bits of FIQStatus?
		if ( io.vic.FIQStatus )
		{
			io.vic.FIQStatus = 0;
			break;
		}
		//find the current IRQ number: which has the highest priority.
		mask = 1;
		nHighestIRQ = 0xffff;
		for ( i = 0; i<=15; i++ )
		{
			nIRQNum = io.vic.VectCntl[i] & 0xf;
			if ( (nIRQNum<<mask) & io.vic.IRQStatus )
			{
				if ( nIRQNum < nHighestIRQ )
					nHighestIRQ = nIRQNum;
			}	
		}
		//If there's at least one IRQ now, clean status and raw
		//status register.
		if ( nHighestIRQ != 0xffff )		
		{
			io.vic.IRQStatus &= ~( nHighestIRQ << mask );
			io.vic.RawIntr &= ~( nHighestIRQ << mask);
		}
		break;
	case 0xfffff034: /* DVAR */
		io.vic.DefVectAddr = data;
		break;
		
	/*Timer0 */
	case 0xe0004000:
		io.timer[0].ir = data;
		if(io.timer[0].ir&0x1){
			io.vic.RawIntr &= ~IRQ_TC0;
		}
		lpc2210_update_int(state);
		break;
	case 0xe0004004:
		io.timer[0].tcr = data;
		break;
	case 0xe0004008:
		io.timer[0].tc = data;
		break;
	case 0xe000400c:
		io.timer[0].pr = data;
		break;
	case 0xe0004010:
		io.timer[0].pc = data;
		break;
	case 0xe0004014:
		io.timer[0].mcr = data;	
    break;
	case 0xe0004018:
		io.timer[0].mr0 = data;
		break;

	/*pll*/
	case 0xe01fc080:
		io.pll.con = data;
		break;
	case 0xe01fc084:
		io.pll.cfg = data;
		break;
	case 0xe01fc088:
		io.pll.stat = data;
		break;
	case 0xe01fc08c:
		io.pll.feed = data;
		break;
		
	/*memory map control*/
	case 0xe01fc040:
		io.mmcr = data;
		break;
		
	/*Pin select control*/
 	case 0xe002c000:
		io.pinsel0 = data;
		break;
	case 0xE002C004:
		io.pinsel1 = data;
		break;
	case 0xE002C014:
		io.pinsel2 = data;
		break;
		
	/*Extend Mem control*/
	case 0xFFE00000:
		io.bcfg[0] = data;
		break;
	case 0xFFE00004:
		io.bcfg[1] = data;
		break;
	case 0xFFE00008:
		io.bcfg[2] = data;
		break;
	case 0xFFE0000c:
		io.bcfg[3] = data;
		break;
	
	/*VIBDIV*/
	case 0xe01fc100:
		io.vibdiv = data;
		break;
		
	/*Real timer*/
	case 0xe0024008:
		io.ccr = data;
		break;
	case 0xe0024080:
                io.preint = data;
                break;
        case 0xe0024084:
                io.prefrac = data;
                break;
	case 0xe0024020:
		io.sec = data;
		break;
	case 0xe0024024:
		io.min = data;
		break;
	case 0xe0024028:
		io.hour = data;
		break;
	case 0xe002402c:
		io.dom = data;
		break;
	case 0xe0024030:
		io.dow = data;
		break;
	case 0xe0024034:
		io.doy = data;
		break;
	case 0xe0024038:
		io.month = data;
		break;
	case 0xe002403c:
		io.year = data;
		break;
			
	/*Mem accelerator regs*/
	case 0xe01fc000:
		io.mamcr = data;
		break;
	case 0xe01fc004:
		io.mamtim = data;
		break;	
		
	default:
		if (addr >=0xe000c000 && addr <= 0xe000c01c) {
			lpc2210_uart_write(state, addr, data,0);
			break;
		}
		if (addr >=0xe0001000 && addr <= 0xe000101c) {
			lpc2210_uart_write(state, addr, data,1);
			break;
		}

		if(addr-0xfffff100 <=0x3c && addr-0xfffff100 >=0){
			io.vic.VectAddr[(addr-0xfffff100)/4] = data;
			break;
		}
		if(addr-0xfffff200 <=0x3c && addr-0xfffff200>=0){
			io.vic.VectCntl[(addr-0xfffff200)/4] = data;
			break;
		}
		printf("ERROR:io_write a non-exsiting addr:addr = %x, data = %x\n", addr, data);
		/*
		fprintf(stderr,"NumInstr %llu,io_write_word unknown addr(1x%08x) = 0x%08x\n", state->NumInstrs, addr, data);*/
		//SKYEYE_OUTREGS(stderr);
		//ARMul_Debug(state, 0, 0);
		break;
	}
}

void lpc2210_mach_init(ARMul_State *state, machine_config_t *this_mach)
{
	//chy 2003-08-19, setprocessor
	ARMul_SelectProcessor(state, ARM_v4_Prop);
        //chy 2004-05-09, set lateabtSig
        state->lateabtSig = HIGH;

	this_mach->mach_io_do_cycle = 		lpc2210_io_do_cycle;
	this_mach->mach_io_reset = 		lpc2210_io_reset;
	this_mach->mach_io_read_byte = 		lpc2210_io_read_byte;
	this_mach->mach_io_write_byte = 	lpc2210_io_write_byte;
	this_mach->mach_io_read_halfword = 	lpc2210_io_read_halfword;
	this_mach->mach_io_write_halfword = 	lpc2210_io_write_halfword;
	this_mach->mach_io_read_word = 		lpc2210_io_read_word;
	this_mach->mach_io_write_word = 	lpc2210_io_write_word;

	this_mach->mach_update_int = 		lpc2210_update_int;

	//ksh 2004-2-7


	state->mach_io.instr = (ARMword *)&io.vic.IRQStatus;
	//*state->io.instr = (ARMword *)&io.intsr;
	//state->io->net_flags = (ARMword *)&io.net_flags;
	//state->mach_io.net_int = (ARMword *)&io.net_int;
}