📄 hardware_reg.h
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/**************************************
define SPI registers
****************************************/
#ifdef SIM
#define BASE_SPI_1 0X00205000
#define PORTF_DIR 0X0020b040
#define PORTF_DATA 0x0020b008
#define PORTF_SEL 0x0020b050
#define DMABASE 0x00221000
#endif
#ifdef FPGA
#define BASE_SPI_1 0X10006000
#define PORTF_DIR 0X1020b040
#define PORTF_DATA 0x1000b008
#define PORTF_SEL 0x1020b050
#endif
#define SPICR (BASE_SPI_1 + 0X00)
#define SPIBR (BASE_SPI_1 + 0X04)
#define SPISR (BASE_SPI_1 + 0X08)
#define SPITR (BASE_SPI_1 + 0X0C)
#define SPIRR (BASE_SPI_1 + 0x10)
#define x_location 0x94
#define y_location 0xD4
#define trigger 0x80
#define ctrlw 0x77
#define bt256 0x0007
#define spif 0x01
//
//dma
//
#define SA (DMABASE + 0X00)
#define DA (DMABASE + 0X04)
#define CTRL (DMABASE + 0X08)
#define DMAENABLE (DMABASE + 0X0C)
#define DMASTATUS (DMABASE + 0X10)
#define DACLW 0XA1040006
#define DACLR 0X91040006
/*********************************************
Define SSI Register
*********************************************/
#ifdef FPGA
#define BASE_SSI 0x40006000
#else
#define BASE_SSI 0x10009000
#endif
#define SSI_CTRLR0 (BASE_SSI + 0x0 )
#define SSI_CTRLR1 (BASE_SSI + 0x04)
#define SSI_SSIENR (BASE_SSI + 0x08)
#define SSI_MWCR (BASE_SSI + 0x0C)
#define SSI_SER (BASE_SSI + 0x10)
#define SSI_BAUDR (BASE_SSI + 0x14)
#define SSI_TXFTLR (BASE_SSI + 0x18)
#define SSI_RXFTLR (BASE_SSI + 0x1C)
#define SSI_TXFLR (BASE_SSI + 0x20)
#define SSI_RXFLR (BASE_SSI + 0x24)
#define SSI_SR (BASE_SSI + 0x28)
#define SSI_IMR (BASE_SSI + 0x2C)
#define SSI_ISR (BASE_SSI + 0x30)
#define SSI_RISR (BASE_SSI + 0x34)
#define SSI_TXOICR (BASE_SSI + 0x38)
#define SSI_RXOICR (BASE_SSI + 0x3C)
#define SSI_RXUICR (BASE_SSI + 0x40)
#define SSI_MSTICR (BASE_SSI + 0x44)
#define SSI_ICR (BASE_SSI + 0x48)
#define SSI_DMACR (BASE_SSI + 0x4C)
#define SSI_DMATDLR (BASE_SSI + 0x50)
#define SSI_DMARDLR (BASE_SSI + 0x54)
//#define SSI_IDR (BASE_SSI + 0x58)
//#define SSI_COMP_VERSION (BASE_SSI + 0x5C)
#define SSI_DR (BASE_SSI + 0x60)
/**************************************
define DMA registers
****************************************/
#define DMACbase 0x11001000
#define DMACIntStatus (DMACbase + 0x0020)
#define DMACIntTCStatus (DMACbase + 0x0050)
#define DMACIntTCClear (DMACbase + 0x0060)
#define DMACIntErrorStatus (DMACbase + 0x0080)
#define DMACIntErrClr (DMACbase + 0x0190)
#define DMACRawIntTCStatus (DMACbase + 0x0070)
#define DMACRawIntErrorStatus (DMACbase + 0x00a0)
#define DMACEnbldChns (DMACbase + 0x00b0)
#define DMACC0SrcAddr (DMACbase+0x000) //DMA channel 0 registers;
#define DMACC0DestAddr (DMACbase+0x004)
#define DMACC0Control (DMACbase+0x00c)
#define DMACC0Configuration (DMACbase+0x010)
#define DMACC0Index (DMACbase+0x014)
#define DMACC1SrcAddr (DMACbase+0x100) //DMA channel 1 registers; R/W
#define DMACC1DestAddr (DMACbase+0x104)
#define DMACC1Control (DMACbase+0x10c)
#define DMACC1Configuration (DMACbase+0x110)
#define DMACC1Index (DMACbase+0x114)
#define DMACC2SrcAddr (DMACbase+0x200) //DMA channel 2 registers; R/W
#define DMACC2DestAddr (DMACbase+0x204)
#define DMACC2Control (DMACbase+0x20c)
#define DMACC2Configuration (DMACbase+0x210)
#define DMACC2Index (DMACbase+0x214)
#define DMACC3SrcAddr (DMACbase+0x300) //DMA channel 3 registers; R/W
#define DMACC3DestAddr (DMACbase+0x304)
#define DMACC3Control (DMACbase+0x30c)
#define DMACC3Configuration (DMACbase+0x310)
#define DMACC3Index (DMACbase+0x314)
#define DMACC4SrcAddr (DMACbase+0x400) //DMA channel 4 registers; R/W
#define DMACC4DestAddr (DMACbase+0x404)
#define DMACC4Control (DMACbase+0x40c)
#define DMACC4Configuration (DMACbase+0x410)
#define DMACC4Index (DMACbase+0x414)
#define DMACC5SrcAddr (DMACbase+0x500) //DMA channel 5 registers; R/W
#define DMACC5DestAddr (DMACbase+0x504)
#define DMACC5Control (DMACbase+0x50c)
#define DMACC5Configuration (DMACbase+0x510)
#define DMACC5Index (DMACbase+0x514)
#define DMA_SCATTER (DMACbase + 0x051c)
#define DMA_GATHER (DMACbase + 0x052c)
/**************************************
define EMI registers
****************************************/
#define EMI_REGBASE 0x11000000 //Sdram sram register base;
#define EMI_NAND_REGBASE 0x11000100 //NAND FLASH register base;
#define EMIADDR_CSACONF ( EMI_REGBASE+0x00 ) //adress of CSACONF register
#define EMIADDR_CSBCONF ( EMI_REGBASE+0x04 ) //adress of CSBCONF register
#define EMIADDR_CSCCONF ( EMI_REGBASE+0X08 ) //adress of CSCCONF register
#define EMIADDR_CSDCONF ( EMI_REGBASE+0X0c ) //adress of CSDCONF register
#define EMIADDR_CSECONF ( EMI_REGBASE+0X10 ) //adress of CSECONF register
#define EMIADDR_CSFCONF ( EMI_REGBASE+0X14 ) //adress of CSFCONF register
#define EMIADDR_SDCONF1 ( EMI_REGBASE+0X18 ) //adress of SDCONF1 register
#define EMIADDR_SDCONF2 ( EMI_REGBASE+0X1c ) //adress of SDCONF2 register
#define EMIADDR_REMAPCONF ( EMI_REGBASE+0X20 ) //adress of REMAPCONF register
#define EMIADDR_NANDADDR1 ( EMI_NAND_REGBASE+0X00 ) //adress of Nand Flash adress register
#define EMIADDR_NANDCOM ( EMI_NAND_REGBASE+0X04 ) //adress of Nand Flash control register
#define EMIADDR_NANDSTATUS ( EMI_NAND_REGBASE+0X0c ) //adress of Nand Flash status register
#define EMIADDR_NANDERRORADDR1 ( EMI_NAND_REGBASE+0X10 ) //adress of Nand Flash error register I
#define EMIADDR_NANDERRORADDR2 ( EMI_NAND_REGBASE+0X14 ) //adress of Nand Flash error register II
#define EMIADDR_NANDCONF1 ( EMI_NAND_REGBASE+0X18 ) //adress of Nand Flash config register1
#define EMIADDR_NANDINTR ( EMI_NAND_REGBASE+0X1c ) //Int clear
#define EMIADDR_NANDFINECC ( EMI_NAND_REGBASE+0X20 ) //ECC complish
#define EMIADDR_NANDIDLE ( EMI_NAND_REGBASE+0X24 ) //Compish register
#define EMIADDR_NANDCONF2 ( EMI_NAND_REGBASE+0X28 ) //adress of Nand Flash config register2
#define EMIADDR_NANDADDR2 ( EMI_NAND_REGBASE+0X2c ) //adress of Nand Flash adress register
#define EMI_NAND_DATA 0x11000200
#define HA_ERRORBASE_EMI 0X28050000
//********************************
//********************************
//PMU
//*****************************
#define PMU_BASE 0x10001000
#define PMU_PLTR (PMU_BASE+0X00)
#define PMU_PMCR (PMU_BASE+0X04)
#define PMU_PUCR (PMU_BASE+0X08)
#define PMU_PSCR (PMU_BASE+0X0C)//OPEN MODULE
#define PMU_PCDR (PMU_BASE+0X10)
#define PMU_PMDR (PMU_BASE+0X14)
#define PMU_PCTR (PMU_BASE+0X18)
#define PMU_CLRWAKUP (PMU_BASE+0X1C)
#define PMU_PDAPB (PMU_BASE+0X20)
//*************************************************
// define I2S_T registers
//*************************************************/
#ifdef FPGA
#define I2S_T_BASE 0x40007000//need modify
#else
#define I2S_T_BASE 0x1000A000//SEP4020
#endif
#define I2S_T_CR (I2S_T_BASE + 0X00)
#define I2S_T_DR (I2S_T_BASE + 0X04)
#define I2S_T_IR (I2S_T_BASE + 0X08)
#define I2S_T_SR (I2S_T_BASE + 0X0C)
#define HALF_FIFO 4
#define MUTE(X) (X << 25)
#define RESET_1(X) (X << 24)
#define ALIGN(X) (X << 23)
#define WS(X) (X << 22)
#define WID(X) (X << 20)
#define DIR(X) (X << 19)
#define MODE(X) (X << 18)
#define MONO(X) (X << 17)
#define STOP(X) (X << 16)
#define DIV(X) X
/*DMAC control reg*/
#define TRANSFERSIZE(X) (X << 14) //transfer data size
#define DI(X) (X << 13)
#define SI(X) (X << 12)
#define DESTSIZE(X) (X << 9 )
#define SOURCESIZE(X) (X << 6 )
#define DESTBURST(X) (X << 3)
#define SOURCEBURST(X) X
#define DMACC0Configuration (DMACbase+0x010)
/*DMAC configuration reg*/
#define CHANNELNUM(X) (X << 15)
#define DESTPERI(X) (X << 11)
#define SRCPERI(X) (X << 7)
#define C(X) (X << 6)
#define ITC(X) (X << 4)
#define IE(X) (X << 3)
#define FLOWCNTRL (X << 1)
#define ENA X
#define EMIADDR_CSC_BASE 0x30300000 //base adress of csb:0x24000000(none now)
#endif //_HARWARE_REG_H
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